Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate stack over the substrate. The semiconductor device structure also includes a spacer element over a sidewall of the gate stack. The spacer element is doped with a dopant, and the dopant reduces a dielectric constant of the spacer element. The spacer element has a first atomic concentration of the dopant near an inner surface of the spacer element adjacent to the gate stack. The spacer element has a second atomic concentration of the dopant near an outer surface of the spacer element. The first atomic concentration of the dopant is different than the second atomic concentration of the dopant.

A system for manufacturing an integrated circuit includes a non-transitory computer readable medium configured to store executable instructions, and a processor coupled to the non-transitory computer readable medium. The processor is configured to execute the executable instructions for placing a set of gate layout patterns on a first layout level, and generating a cut feature layout pattern extending in the first direction. The set of gate layout patterns correspond to fabricating a set of gate structures of the integrated circuit. The cut feature layout pattern is on the first layout level, and overlap each of the layout patterns of the set of gate layout patterns at a same position in the second direction. The cut feature layout pattern identifies a location of a removed portion of a gate structure of the set of gate structures.

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.

A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.

The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.