H01L21/283

High voltage isolation structure and method

Described examples include a microelectronic device with a high voltage capacitor that includes a high voltage node, a low voltage node, a first dielectric disposed between the low voltage node and the high voltage node, a first conductive plate disposed between the first dielectric and the high voltage node, and a second dielectric disposed between the first conductive plate and the high voltage node.

Semiconductor Device with a Passivation Layer and Method for Producing Thereof

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

Semiconductor Device with a Passivation Layer and Method for Producing Thereof

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers include outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer.

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
20210351291 · 2021-11-11 ·

A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
20210351291 · 2021-11-11 ·

A metal oxide semiconductor field effect transistor and a method for manufacturing the same are provided. The metal oxide semiconductor field effect transistor includes a substrate structure, doped regions, an oxide layer structure, semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer forms a plurality of trenches along a first direction. Any two adjacent trenches form a pitch therebetween, and the pitches formed between the trenches are increased along the first direction. The doped regions are formed at bottoms of the trenches. The oxide layer structure is formed on inner walls of the trenches and a surface of the epitaxial layer. The semiconductor layer structures are respectively formed in the trenches. The dielectric layer structure is formed on the oxide layer structure. The metal structure is formed on the dielectric layer structure.

Metal oxide thin film transistor and manufacturing method thereof
11171247 · 2021-11-09 ·

Disclosed is a metal oxide thin film transistor and a manufacturing method thereof. By disposing a portion of the source and a portion of the drain in the same layer as the first insulating layer, the reflection of the ultraviolet light by the source, the drain and the first insulating layer can be blocked from entering the conductive channel. Therefore, a threshold voltage shift of the metal oxide thin film transistor under irradiation of ultraviolet light to the conductive channel can be prevented, and the threshold voltage stability and display quality are improved.

Metal oxide thin film transistor and manufacturing method thereof
11171247 · 2021-11-09 ·

Disclosed is a metal oxide thin film transistor and a manufacturing method thereof. By disposing a portion of the source and a portion of the drain in the same layer as the first insulating layer, the reflection of the ultraviolet light by the source, the drain and the first insulating layer can be blocked from entering the conductive channel. Therefore, a threshold voltage shift of the metal oxide thin film transistor under irradiation of ultraviolet light to the conductive channel can be prevented, and the threshold voltage stability and display quality are improved.

Additive manufacturing processes and additively manufactured products

A technique to additively print onto a dissimilar material, especially ceramics and glasses (e.g., semiconductors, graphite, diamond, other metals) is disclosed herein. The technique enables manufacture of heat removal devices and other deposited structures, especially on heat sensitive substrates. It also enables novel composites through additive manufacturing. The process enables rapid bonding, orders-of-magnitude faster than conventional techniques.

Additive manufacturing processes and additively manufactured products

A technique to additively print onto a dissimilar material, especially ceramics and glasses (e.g., semiconductors, graphite, diamond, other metals) is disclosed herein. The technique enables manufacture of heat removal devices and other deposited structures, especially on heat sensitive substrates. It also enables novel composites through additive manufacturing. The process enables rapid bonding, orders-of-magnitude faster than conventional techniques.

Trench gate trench field plate vertical MOSFET

A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.