Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.

Patterning methods for forming patterned device substrates are provided. Also provided are devices made using the methods. The methods utilize photoresist features have re-entrant profiles to form a secondary metal hard mask that can be used to pattern an underlying device substrate.

A capacitor that includes a substrate having a main surface with at least one of a recess or a projection, a dielectric film extending along the at least one of the recess or the projection and having an equivalent oxide thickness of 600 nm or more, and a conductor film covering at least part of the dielectric film.

A capacitor that includes a substrate having a main surface with at least one of a recess or a projection, a dielectric film extending along the at least one of the recess or the projection and having an equivalent oxide thickness of 600 nm or more, and a conductor film covering at least part of the dielectric film.

Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

A method for manufacturing a solid state device with a self-forming nanogap includes patterning a first metallic layer (M1) to form a first electrode on a substrate; depositing a self-assembling monolayer, SAM, layer over and around the first electrode; forming a second metallic layer (M2) in contact with the SAM layer and the substrate; and touchlessly removing parts of the second metallic layer (M2) that is formed directly above the SAM layer, to form a second electrode, and a nanogap between the first electrode and the second electrode.

A method for manufacturing a solid state device with a self-forming nanogap includes patterning a first metallic layer (M1) to form a first electrode on a substrate; depositing a self-assembling monolayer, SAM, layer over and around the first electrode; forming a second metallic layer (M2) in contact with the SAM layer and the substrate; and touchlessly removing parts of the second metallic layer (M2) that is formed directly above the SAM layer, to form a second electrode, and a nanogap between the first electrode and the second electrode.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.