Systems and method are provided for depositing metal on GaN transistors after gate formation using a metal nitride Schottky gate. Embodiments of the present disclosure use a “diamond last” process using thermally stable metal nitride gate electrodes to enable thicker heat spreading films and facilitate process integration. In an embodiment, the “diamond last” process with high thermal conductivity diamond is enabled by the integration of thermally stable metal-nitride gate electrodes.

Provided herein are processes for transferring high quality large-area graphene layers (e.g., single-layer graphene) to a flexible substrate based on preferential adhesion of certain thin metallic films to graphene followed by lamination of the metallized graphene layers to a flexible target substrate in a process that is compatible with roll-to-roll manufacturing, providing an environmentally benign and scalable process of transferring graphene to flexible substrates.

Provided herein are processes for transferring high quality large-area graphene layers (e.g., single-layer graphene) to a flexible substrate based on preferential adhesion of certain thin metallic films to graphene followed by lamination of the metallized graphene layers to a flexible target substrate in a process that is compatible with roll-to-roll manufacturing, providing an environmentally benign and scalable process of transferring graphene to flexible substrates.

A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal wiring layer including copper (7S, 7D); a metal oxide film including copper (8) arranged on an upper surface of the at least one metal wiring layer (7S, 7D); an insulating layer (11) covering at least one metal wiring layer with the metal oxide film (8) interposed therebetween; and a conductive layer (19) in direct contact with a portion of the at least one metal wiring layer, without the metal oxide film (8) interposed therebetween, in an opening formed in the insulating layer (11).

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

A selective film forming method includes: preparing a substrate including a first film having a first surface and a second film having a second surface, the second film being different from the first film; selectively adsorbing a secondary alcohol gas and/or a tertiary alcohol gas to the second surface; and selectively forming a film on the first surface by supplying at least a raw material gas.

Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.