H01L21/441

VERTICAL STACKS OF LIGHT EMITTING DIODES AND CONTROL TRANSISTORS AND METHOD OF MAKING THEREOF
20200373349 · 2020-11-26 ·

A light emitting device includes a vertical stack of a light emitting diode and a field effect transistor that controls the light emitting diode. An isolation layer is present between the light emitting diode and the field effect transistor, and an electrically conductive path electrically shorts a node of the light emitting diode to a node of the field effect transistor. The field effect transistor may include an indium gallium zinc oxide (IGZO) channel and may be located over the isolation layer. Alternatively, the field effect transistor may be a high-electron-mobility transistor (HEMT) including an epitaxial semiconductor channel layer and the light emitting diode may be located over the HEMT.

Low resistance contact interlayer for semiconductor devices

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.

Low resistance contact interlayer for semiconductor devices

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. An n-type material is formed on or in the p-doped layer. The n-type material includes an oxide of a II-VI material. An oxygen scavenging interlayer is formed on the n-type material. An aluminum contact is formed in direct contact with the oxygen scavenging interlayer to form an electronic device.

HIGH VOLTAGE, LOW PRESSURE PLASMA ENHANCED ATOMIC LAYER DEPOSITION
20200350179 · 2020-11-05 ·

Atomic layer deposition (ALD) methods and barrier films are disclosed. A method of performing ALD includes placing a substrate proximal an electrode coupled to a power supply, exposing the substrate to an oxygen-containing gas or a nitrogen-containing gas at or below 0.8 Torr, and applying, with the power supply, a voltage to the electrode of at least 700 Volts to induce a plasma state in the oxygen-containing gas or the nitrogen-containing gas proximal the substrate. High quality barrier films can be made with the methods.

HIGH VOLTAGE, LOW PRESSURE PLASMA ENHANCED ATOMIC LAYER DEPOSITION
20200350179 · 2020-11-05 ·

Atomic layer deposition (ALD) methods and barrier films are disclosed. A method of performing ALD includes placing a substrate proximal an electrode coupled to a power supply, exposing the substrate to an oxygen-containing gas or a nitrogen-containing gas at or below 0.8 Torr, and applying, with the power supply, a voltage to the electrode of at least 700 Volts to induce a plasma state in the oxygen-containing gas or the nitrogen-containing gas proximal the substrate. High quality barrier films can be made with the methods.

Semiconductor device and fabricating method thereof

A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

Semiconductor device and fabricating method thereof

A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.

Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Semiconductor device and method for manufacturing semiconductor device

In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.