Patent classifications
H01L21/461
Substrate processing method and substrate processing apparatus
A substrate processing method is a method of processing a substrate on which a metal-containing liquid for a film below a resist is applied, wherein prior to a heating process of performing a heat treatment on the substrate applied with the metal-containing liquid, the substrate processing method includes: a deprotection promoting process of promoting deprotection of functional groups in a material for the film included in the substrate on which the metal-containing liquid has been applied; a solvent removing process of removing a solvent included in the metal-containing liquid on the substrate; and a moisture absorbing process of bringing a surface of the substrate into contact with moisture.
Flexible electrically conductive pastes and devices made therewith
This invention provides a polymer thick film electrically conductive paste composition, comprising conductive metal powder, a resin blend of polyol and phenoxy resin, blocked aliphatic polyisocyanate and one or more polar, aprotic solvents. In one embodiment the paste composition is used to form electrically conductive adhesive. In another embodiment the paste composition is used to form an electrically conductive polymer thick film.
Semiconductor wafer with low defect count and method for manufacturing thereof
A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.
Semiconductor wafer with low defect count and method for manufacturing thereof
A semiconductor wafer and method for manufacturing thereof are provided. The semiconductor wafer includes a handling substrate and a silicon layer over the handling substrate and having a {111} facet at an edge of a top surface of the silicon layer. The a defect count on the top surface of the silicon layer is less than about 15 each semiconductor wafer. The method includes the following operations: a semiconductor-on-insulator (SOI) substrate is provided, wherein the SOI substrate has a handling substrate, a silicon layer over the handling substrate, and a silicon germanium layer over the silicon layer; and the silicon germanium layer is etched at a first temperature with hydrochloric acid to expose a first surface of the silicon layer.
FETs and methods of forming FETs
An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
FETs and methods of forming FETs
An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
Using absolute Z-height values for synergy between tools
A semiconductor review tool receives absolute Z-height values for the semiconductor wafer, such as a semiconductor wafer with a beveled edge. The absolute Z-height values can be determined by a semiconductor inspection tool. The semiconductor review tool reviews the semiconductor wafer within a Z-height based on the absolute Z-height values. Focus can be adjusted to within the Z-height.
Using absolute Z-height values for synergy between tools
A semiconductor review tool receives absolute Z-height values for the semiconductor wafer, such as a semiconductor wafer with a beveled edge. The absolute Z-height values can be determined by a semiconductor inspection tool. The semiconductor review tool reviews the semiconductor wafer within a Z-height based on the absolute Z-height values. Focus can be adjusted to within the Z-height.
Display substrate, method for preparing the same, and display device
The present disclosure provides a display substrate, a method for preparing the same, and a display device including the display substrate. The method includes: forming a conductive layer; forming a first photoresist pattern and a second photoresist pattern on the conductive layer, in which the adhesion between the first photoresist pattern and the conductive layer is less than the adhesion between the second photoresist pattern and the conductive layer; and etching the conductive layer by using the first photoresist pattern and the second photoresist pattern as masks to form a first conductive pattern and a second conductive pattern, respectively, in which a line width difference between the first conductive pattern and the first photoresist pattern is greater than a line width difference between the second conductive pattern and the second photoresist pattern.
CHEMICAL MECHANICAL POLISHING (CMP) COMPOSITION FOR HIGH EFFECTIVE POLISHING OF SUBSTRATES COMPRISING GERMANIUM
Disclosed herein is a chemical mechanical polishing (CMP) composition (Q) containing (A) inorganic particles, (B) a compound of general formula (I) below, and (C) an aqueous medium, in which the composition (Q) has a pH of from 2 to 6.
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