In one embodiment of the present invention, an etching method for a substrate to be processed comprises: (a1) a step in which etchant gas is supplied into a processing container than accommodates a substrate to be processed; (b1) a step in which the inside of the processing container is evacuated; (c1) a step in which a noble gas is supplied into the processing container; and (d1) a step in which microwaves are supplied into the processing container so as to excite the plasma of the noble gas inside the processing container. The sequential process including the step of supplying the etchant of supplying the etchant gas, the evacuating step, the step of supplying the noble gas, and the step of exciting the plasma of the noble gas may be repeated.

Disclosed are sulfur-containing compounds for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The plasma etching compounds may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.

A first etching rate of the first conductive film is calculated by acquiring correlation between an opening ratio of an etching mask and an etching rate of an etching target film, and then, performing a first dry etching to a first conductive film formed on a first wafer. Next, a second etching mask is formed on a second conductive film formed on a second wafer, and an etching time of the second conductive film is determined from the correlation between the opening ratio and the etching rate, the first etching rate, and a film thickness of the second conductive film when the second conductive film is subjected to a second dry etching in time-controlled etching.

A method for forming a semiconductor structure including forming a plurality of mandrel lines on a first dielectric layer and forming one or more groups of discontinuous mandrel line pairs with a first mask. The method further includes disposing a second dielectric layer, and forming dielectric spacers on sidewalls of the mandrel lines and the discontinuous mandrel line pairs. The method further includes removing the mandrel lines and the discontinuous mandrel line pairs to form spacer masks, forming one or more groups of blocked regions using a second mask, and forming openings extended through the first dielectric layer with a conjunction of the spacer masks and the second mask. The method also includes removing the spacer masks and the second mask, disposing an objective material in the openings, and forming objective lines with top surfaces coplanar with the top surfaces of the first dielectric layer.

A method for forming a plurality of precision holes in a substrate by drilling, including affixing a sacrificial cover layer to a surface of the substrate, positioning a laser beam in a predetermined location relative to the substrate and corresponding to a desired location of one of the plurality of precision holes, forming a through hole in the sacrificial cover layer by repeatedly pulsing a laser beam at the predetermined location, and pulsing the laser beam into the through hole formed in the sacrificial cover layer. A work piece having precision holes including a substrate having the precision holes formed therein, wherein a longitudinal axis of each precision hole extends in a thickness direction of the substrate, and a sacrificial cover layer detachably affixed to a surface of the substrate, such that the sacrificial cover layer reduces irregularities of the precision holes.

The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.

The invention provides chemical-mechanical polishing compositions and methods of chemically-mechanically polishing a substrate, especially a substrate comprising a silicon oxide layer, with the chemical-mechanical polishing compositions. The polishing compositions comprise first abrasive particles, wherein the first abrasive particles are wet-process ceria particles, have a median particle size of about 75 nm to about 200 nm, and are present in the polishing composition at a concentration of about 0.005 wt. % to about 2 wt. % a functionalized heterocycle, a cationic polymer selected from a quaternary amine, is cationic polyvinyl alcohol, and a cationic cellulose, optionally a carboxylic acid, a pH-adjusting agent, and an aqueous carrier, and have a pH of about 1 to about 6.

Provided are slurry for polishing cobalt and a substrate polishing method. The slurry includes an abrasive configured to perform the polishing, the abrasive comprising zirconium oxide particles, a dispersing agent configured to disperse the abrasive, and a polishing accelerator configured to accelerate the polishing. The polishing accelerator includes an organic acid containing an amine group and a carboxylic group. According to the slurry in accordance with an exemplary embodiment, a polishing rate of the cobalt may increases without using an oxidizing agent, and local corrosion defects on a surface of the cobalt may be suppressed.

An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.

An SGT is formed that includes Si pillars. The SGT includes WSi2 layers serving as wiring alloy layers and constituted by first alloy regions that are connected to the entire peripheries of impurity regions serving as sources or drains located in lower portions of the Si pillars, are formed in a self-aligned manner with the impurity regions in a tubular shape, and contain the same impurity atom as the impurity regions and a second alloy region that is partly connected to the peripheries of the first alloy regions and contains the same impurity atom as the impurity regions.