A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

An electronic element mounting substrate includes a base body, an electrode, and a pad. The base body has a frame shape, and includes a first frame section and a second frame section, the second frame section being disposed on the first frame section and including an inner surface protruding further inward than an inner surface of the first frame section. The electrode is disposed on a bottom surface of the first frame section of the base body. The pad is disposed on a bottom surface of a protruding part of the second frame section, and is electrically connected to the electrode. A groove extending in a vertical direction is formed in an inner surface of the protruding part of the second frame section of the base body.

Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.

The present invention includes: a substrate 3, a rectangular frame-shaped substrate bank section 5 provided on the substrate 3 and including four corner portions 5A, and a metal layer 9 provided on a top surface 5Aa of the substrate bank section 5. A top surface 5Aa of the corner portions 5A of the substrate bank section 5 may have an inclined portion S slanted downward. An electronic component housing package may have a lid welded onto the metal layer 9 provided on the substrate bank section 5 of the electronic component storage substrate.

A ceramic substrate manufacturing method and a ceramic substrate manufactured thereby, may include a seed layer, a brazing filler layer, and a metal foil that are laminated on a ceramic substrate and that are brazed such that the metal foil is firmly bonded to the ceramic substrate by a brazing joint layer. Such methods and devices may substantially improve the adhesion of the metal foil and the ceramic substrate.

A method of manufacturing a ceramic package is provided. An electrically conductive paste is applied to an inside of the first hole and an inside of the second hole of a ceramic green sheet. A ceramic member including first and second electrically conductive members is formed by burning the ceramic green sheet. The ceramic member is divided so as to divide each of the first and second electrically conductive members. A distance between first and second connecting portions is smaller than each of a length of the first connecting portion in a first direction and a length of the second connecting portion in a second direction. The length of the first connecting portion in the first direction is larger than a length of the first connecting portion in a third direction. The length of the second connecting portion has a similar relation.

Articles including a glass-based substrate with holes, semiconductor packages including an article with holes, and methods of fabricating holes in a substrate are disclosed. In one embodiment, an article includes a glass-based substrate having a first surface, a second surface, and at least one hole extending from the first surface. The at least one hole has an interior wall having a surface roughness R.sub.a that is less than or equal to 1 m. The at least one hole has a first opening having a first diameter that is present the first surface. A first plane is defined by the first surface of the glass-based substrate based on an average thickness of the glass-based substrate. A ratio of a depression depth to the first diameter of the at least one hole is less than or equal to 0.007.

A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

A power device includes a substrate comprising a polycrystalline ceramic core, a first adhesion layer coupled to the polycrystalline ceramic core, a barrier layer coupled to the first adhesion layer, a bonding layer coupled to the barrier layer, and a substantially single crystal layer coupled to the bonding layer. The power device also includes a buffer layer coupled to the substantially single crystal layer and a channel region coupled to the buffer layer. The channel region comprises a first end, a second end, and a central portion disposed between the first end and the second end. The channel region also includes a channel region barrier layer coupled to the buffer layer. The power device further includes a source contact disposed at the first end of the channel region, a drain contact disposed at the second end of the channel region, and a gate contact coupled to the channel region.