An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.

Provided are a ceramic substrate and a method of manufacturing the same, which suppress a warpage phenomenon caused by a difference in volumes occupied by upper and lower metal layers of a ceramic base material and controls areas of the upper and lower metal layers especially when thicknesses of the upper and lower metal layers on the ceramic base material are equal to each other, thereby reducing a defect rate of the ceramic substrate.

Provided is a semiconductor device capable of suppressing misalignment of a brazing material when bonding a metal terminal to a metal circuit pattern. The semiconductor device includes an insulating substrate with a metal circuit pattern formed in a surface thereof and a metal terminal bonded onto the metal circuit pattern via a hard brazing material, in which protrusions are provided on the metal circuit pattern, and the protrusions are in contact with the hard brazing material.

Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a circuit board is provided that has a substrate with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.

Color unevenness generated on a surface of a silicon nitride substrate is reduced. A silicon nitride substrate formed by nitriding silicon containing in a sheet-shaped green body includes a first surface and a second surface opposite to the first surface. In this case, when color difference between a center and an edge of at least one surface of the first surface and the second surface is expressed to be “ΔE*ab”, a relation “ΔE*ab≤1.5” is established.

A described example includes: a ceramic package having a board side surface and an opposite top side surface; a heat slug mounted to the board side surface of the ceramic package, forming a bottom surface in a die cavity; leads mounted to conductive lands on the ceramic package; sidewall metallization extending from the conductive lands and covering a portion of one of the sides of the ceramic package; copper tungsten alloy conductor layers formed in the ceramic package and spaced by dielectric layers; bond fingers formed of a conductor layer and extending to the die cavity; a semiconductor device mounted over the heat slug, and having bond pads on a device side surface facing away from a surface of the heat slug; electrical connections between bond pads on the semiconductor device and the bond fingers; and a lid mounted to the top side surface of the ceramic package.

The present disclosure has been conceived to solve such a problem, and it is an object of the present disclosure to provide a semiconductor device enabling reduction in cost. A semiconductor device according to the present disclosure includes: a base plate; an insulating substrate disposed over the base plate; a semiconductor chip disposed over the insulating substrate; a first resin case and a second resin case attached to the base plate to enclose the insulating substrate and the semiconductor chip, and fitted together; and a sealing material to seal the insulating substrate and the semiconductor chip, wherein the first resin case and the second resin case are formed of resin materials having different comparative tracking indices.

An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.

Embodiments of the disclosure relate to a method for fabricating semiconductor-on-insulator (SemOI) electronic components. In the method, a device wafer is bonded to a handling wafer. The device wafer includes a semiconductor device layer and a buried oxide layer. A substrate is adhered to the handling wafer. The substrate is a glass or a ceramic, and bonding occurs at an interface between the semiconductor device layer and the substrate. Material is removed from the device wafer to expose the buried oxide layer. The substrate is debonded from the handling wafer so as to provide an SemOI electronic component including the substrate, the semiconductor device layer, and the buried oxide layer.

There is provided a substrate holder. The substrate holder that holds a substrate and is installed in a device for transferring the substrate. The substrate holder includes: a ceramic main body; and a heat pipe which includes a flow path of a working fluid. The flow path is formed inside the main body.