The present invention provides a power semiconductor module, including a substrate having an electric insulating main layer being provided with a structured top metallization and with a bottom metallization, wherein the top metallization is provided with at least one power semiconductor device and at least one contact area, wherein the main layer together with its top metallization and the at least one power semiconductor device is embedded in a mold compound such that the mold compound includes at least one opening for contacting the at least one contact area, and wherein power semiconductor module includes a housing with circumferential side walls, wherein the side walls are positioned above the main layer of the substrate so that the side walls are only present in a space above a plane through the main layer of the substrate.

A method of evaluating the driving behavior in a vehicle. The method includes determining values of a plurality of parameters of the operation of a first vehicle in a first road segment, determining values of the plurality of parameters for one or more second vehicles in a second road segment having similar properties to those of the first road segment, comparing the determined values of the first vehicle and the one or more second vehicles and providing an evaluation of the driving behavior of the first vehicle, responsive to the comparison.

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.

Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

A printed circuit board comprising: a first insulating layer; a first wiring layer disposed on one surface of the first insulating layer; and a bump at least partially disposed in the first insulating layer and connected to the first wiring layer. The bump at least partially protrudes from the other surface of the first insulating layer, opposite to the one surface of the first insulating layer.

A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

A semiconductor structure includes: a base; a conductive column, which is at least located in the base; an electric connection layer, which is connected to an end part of the conductive column. The end part, towards the electric connection layer, of the conductive column has a first protruding part and at least one groove defined by the first protruding part, the electric connection layer has a second protruding part at a position corresponding to the groove, and the second protruding part is embedded in the groove.

Systems and methods for bonding an electronic component to substrate with a rough surface. The method comprising: disposing an insulating adhesive on the substrate; applying heat and pressure to the insulating adhesive to cause the adhesive to flow into at least one opening formed in the substrate; curing the insulating adhesive to form a pad that is at least partially embedded in the substrate and comprises a planar smooth surface that is exposed; disposing at least one trace on the planar smooth surface of the pad; depositing an anisotropic conductive material on the pad so as to at least cover the at least one trace; placing the electronic component on the pad so that an electrical coupling is formed between the electronic component and the at least one trace; and bonding the electronic component to the substrate by curing the anisotropic conductive material.