A reconstituted substrate, a packaged assembly comprising a reconstituted substrate, and methods for fabricating a reconstituted substrate. An example reconstituted substrate generally includes multiple package-level substrates implemented with different substrate technologies and held together. An example method for fabricating a reconstituted substrate generally includes forming multiple package-level substrates implemented with different substrate technologies, arranging the multiple package-level substrates, and adding a material to hold the multiple package-level substrates together.

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.

Circuit boards, LED lighting systems and methods of manufacture are described. A circuit board includes a ceramic carrier and a body on the ceramic carrier. The body includes dielectric layers and slots formed completely through a thickness of the dielectric layers. The slots are filled with a dielectric material. A conductive pad is provided on a surface of each of the slots opposite the ceramic carrier.

Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use an encapsulant on solder balls in combination with a dam or a trench to control the distribution of an under-fill material between one or more components and a packaging substrate. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant reduces the tendency of the under-fill material to wick around the solder balls by capillary action which can prevent or limit the capillary under-fill material from flowing onto or contacting other components. The dam or trench aids in retaining the under-fill material within a keep out zone to prevent or limit the under-fill material from contacting other components.

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a first metallization line, a second metallization line, a first isolation feature, a second isolation feature, a profile modifier, and a contact feature. The first metallization line and the second metallization line extend along a first direction. The first isolation feature and the second isolation feature are disposed between the first metallization line and the second metallization line. The first metallization line, the second metallization line, the first isolation feature and the second isolation feature define an aperture. The profile modifier is disposed within the aperture to modify a profile of the aperture in a plan view. The contact feature is disposed within the aperture.

Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures. The second angled conductive layers are positioned over the second transmission lines and first dielectric having a second pattern of second triangular structures, where the second pattern is shaped as a coaxial interconnects enclosed with second triangular structures and portions of first dielectric.

An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.

A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on the insulating layer; and a first protective layer disposed on the insulating layer, wherein the first protective layer includes a first opening vertically overlapping at least a part of an upper surface of the circuit pattern; wherein an inner wall of the first protective layer constituting the first opening includes: a first portion having a first inclination, and a second portion disposed on the first portion and having a second inclination different from the first inclination, and wherein the first portion overlaps the circuit pattern in a horizontal direction.

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.