An electronic component embedded substrate includes a core structure including a first insulating body and core wiring layers and having a cavity and having a stopper layer disposed as a bottom surface; an electronic component disposed in the cavity and attached to the stopper layer; and a build-up structure including a second insulating body covering at least a portion each of the core structure and the electronic component and filling at least a portion of the cavity, and build-up wiring layers wherein the stopper layer has a first region in which a portion of one surface is exposed from the first insulating body and a second region in which the other portion of one surface is covered with the first insulating body, and a surface roughness of one surface of the stopper layer in the first region is greater than that of the stopper layer in the second region.

A method of manufacturing a glass article comprises: (A) forming a first layer of catalyst metal on a glass substrate; (B) heating the glass substrate; (C) forming a second layer of an alloy of a first metal and a second metal on the first layer; (D) heating the glass substrate, thereby forming a glass article comprising: (i) the glass substrate; (ii) an oxide of the first metal covalently bonded thereto; and (iii) a metallic region bonded to the oxide, the metallic region comprising the catalyst, first, and second metals. In embodiments, the method further comprises (E) forming a third layer of a primary metal on the metallic region; and (F) heating the glass article thereby forming the glass article comprising: (i) the oxide of the first metal covalently bonded the glass substrate; and (ii) a new metallic region bonded to the oxide comprising the catalyst, first, second, and primary metals.

A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

A flexible circuit board and an electronic device including a flexible circuit board are provided. The flexible circuit board may include a substrate having a bending area and a non-bending area, a wiring pattern layer provided on the bending area and the non-bending area, a plating layer provided on the wiring pattern layer and including an open area in an area corresponding to the bending area, and a protective layer that directly contacts one surface of the wiring pattern layer exposed at the open area and a side surface of the plating layer. The protective layer may have a larger thickness than a thickness of the plating layer.

The technique described herein includes a device to address the electrical performance (e.g. signal integrity) degradation ascribed to electromagnetic interference and/or crosstalk coupling occur at tightly coupled (e.g. about 110 μm pitch or less) interconnects, including the first level (e.g. the interconnection between a die and a package substrate). In some embodiments, this invention provides a conductive layer with a plurality of cavities to isolate electromagnetic coupling and/or interference between adjacent interconnects for electronic device performance scaling. In some embodiments, at least one interconnect joint is coupled to the conductive layer, and at least one interconnect joint is isolated from the conductive layer by a dielectric lining at least one of the cavities, the conductive layer being associated to a ground reference voltage by the interconnect joint coupled to the conductive layer.

An electronic package is provided, in which a circuit board and a circuit block are embedded in an encapsulating layer at a distance to each other, and circuit structures are formed on the two opposite surfaces of the encapsulating layer with electronic components arranged on one of the circuit structures. The circuit block and the circuit board embedded in the encapsulating layer are spaced apart from each other to allow to separate current conduction paths. As such, the circuit board will not overheat, and issues associated with warpage of the circuit board can be eliminated. Moreover, by embedding the circuit block and the circuit board in the encapsulating layer at a distance to each other, the structural strength of the encapsulating layer can be improved.

One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity.

Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate including a first metal layer and a second metal layer; a cavity in the substrate, wherein a portion of the first metal layer in the substrate and a portion of the second metal layer in the substrate are exposed in the cavity; and a bridge component in the cavity, the bridge component includes a first conductive contact at a first face and a second conductive contacts at an opposing second face, wherein the second face of the bridge component is between the first face of the bridge component and a bottom surface of the cavity in the substrate, and wherein the second conductive contact is electrically coupled to the portion of the first metal layer in the cavity.