A method of manufacturing a component carrier includes forming a stack with electrically conductive layer structures and at least one electrically insulating layer structure; configuring the stack as a redistribution structure for transferring between a smaller pitch on one side of the stack towards a larger pitch on an opposing other side of the stack; arranging a first stiffening structure and a second stiffening structure in opposing surface regions of the stack. A component carrier and an electric device manufactured with the method exhibit improved stiffness and signal integrity.

A flexible circuit board includes a substrate a, a wiring pattern layer provided on the first surface of the substrate, a plating layer provided on the wiring pattern layer and including an open area, and a protective layer that contacts parts of the wiring pattern layer, the plating layer, and the substrate. The protective layer has a larger thickness than a thickness of the plating layer. The first protective layer includes a first overlapping region in which the plating layer and protective layer are in contact with each and a second overlapping region in which the plating layer and the protective layer are in contact with each other. A width of the first overlapping region may be different from a width of the second overlapping region, and each of the widths of the first and second overlapping regions is larger than a thickness of the plating layer.

Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.

A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.

A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m.Math.k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.

Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity.

An electronic component-embedded substrate includes a core layer, a first cavity formed in the core layer, a heat dissipating member disposed in the first cavity and having a second cavity, and an electronic component disposed in the second cavity. The heat dissipating member includes a carbon fiber reinforced polymer (CFRP).

A security chip includes: a first medium layer; a second medium layer disposed on the first medium layer, where the first medium layer is an optically denser medium relative to the second medium layer, and a roughness of an upper surface of the first medium layer is greater than or equal to a preset threshold, so that light entering the second medium layer from the first medium layer is able to be totally reflected and/or scattered; and a semiconductor chip disposed on the second medium layer. Based on the above technical solution, light incident from a lower surface of the first medium layer is able to be totally reflected or scattered by the upper surface of the first medium layer, so that most of light cannot reach a logic or storage area on the front of the security chip, thereby achieving the purpose of resisting a laser attack.

A component carrier includes a stack having at least one electrically conductive layer structure, a first electrically insulating layer structure and a second electrically insulating layer structure. The first electrically insulating layer structure is made of a material which has first physical properties. The second electrically insulating layer structure is made of another material which has second physical properties differing from the first physical properties. The first electrically insulating layer structure and the second electrically insulating layer structure are at least partially in direct physical contact with each other. A method of manufacturing a component carrier is also disclosed.