A semiconductor device includes a laminated body, a semiconductor element, and a cooler. The laminated body includes a first conductor layer, a first insulator layer, a second conductor layer, a second insulator layer, and a third conductor layer. The first conductor layer, the first insulator layer, the second conductor layer, the second insulator layer and the third conductor layer are laminated. The first insulator layer is arranged between the first conductor layer and the second conductor layer, and electrically insulates the first conductor layer from the second conductor layer. The second insulator layer is arranged between the second conductor layer and the third conductor layer, and electrically insulates the third conductor layer from the second conductor layer. The semiconductor element is mounted on the first conductor layer. The cooler is connected to the third conductor layer.

A semiconductor apparatus includes: a base plate; an insulating circuit board including a ceramic substrate, a circuit pattern formed on an upper surface of the ceramic substrate, a metal layer formed on a lower surface of the ceramic substrate and fixed on an upper surface of the base plate with a first joint material; a semiconductor device having a first surface fixed on the circuit pattern with a second joint material and a second surface which is an opposite surface of the first surface; a lead frame fixed on the second surface with a third joint material; and a case fixed to an outer edge portion of the base plate and enclosing the semiconductor device, wherein restoring force acts on the insulating circuit board in a direction of warpage that is convex upward, and restoring force acts on the base plate in a direction of warpage that is convex downward.

Electronic assemblies and methods of assembly are described. In an embodiment, an electronic assembly includes a stiffener structure shear bonded to an opposite side of a module substrate from a ball grid array (BGA) package. The stiffener structure may be shear bonded at elevated temperature after bonding of the BGA package to lock in a flat or near-flat surface contour of the module substrate.

A semiconductor apparatus includes a first connection terminal and a second connection terminal, a drive circuit including one or more power semiconductor elements, a control circuit to control the one or more power semiconductor elements, a circuit substrate, a passive element on the circuit substrate, and a first bus bar and a second bus bar. The first bus bar includes a first body including a path electrically connecting the first connection terminal to the drive circuit, and a first protrusion protruding toward the circuit substrate against the first body. The second bus bar includes a second body including a path electrically connecting the second connection terminal and the drive circuit, and a second protrusion protruding toward the circuit substrate against the second body. The passive element is electrically connected to the first protrusion and to the second protrusion.

A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path.

A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.

There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

This hermetic sealing lid member (10) is made of a clad material (20) including a silver brazing layer (21) that contains Ag and Cu and a first Fe layer (22) bonded onto the silver brazing layer and made of Fe or an Fe alloy. The hermetic sealing lid member is formed in a box shape including a recess portion (13) by bending the clad material.

An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode portion located outside the die bond portion; a ceramic substrate buried in the sealing resin layer; and an electronic component disposed on the die bond portion. When viewed in plan, the die bond portion and the ceramic substrate are partially overlapped to be in contact with each other, and the terminal electrode portion and the ceramic substrate are partially overlapped to be in contact with each other. The electronic component is electrically connected to the terminal electrode portion. The metal member includes a first plating layer and a second plating layer, and the average crystal grain diameter of the first plating layer is smaller than the average crystal grain diameter of the second plating layer.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.