The present disclosure is directed to a method of manufacturing semiconductor devices that includes providing a substrate such as a leadframe having a non-etched adhesion promoter, NEAP layer over the die mounting surface and attaching thereon a semiconductor die having an attachment surface including a first and a second die areas that are wettable by electrically conductive solder material. The NEAP layer is selectively removed, e.g., via laser ablation, from the first substrate area and the second substrate area of the die mounting surface of the substrate. The first substrate area and the second substrate area of the substrate having complementary shapes with respect to the first and second die areas of the semiconductor die. Electrically conductive solder material is dispensed on the first and second substrate areas of the substrate. A semiconductor die is flipped onto the substrate with the first die area and the second die area aligned with the first substrate area and the second substrate area of the substrate having the solder material dispensed thereon. The electrically conductive solder material thus provides electrical coupling of: the first die area and the first substrate area, and the second die area and the second substrate area.

A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.

In a semiconductor device, a first skirt portion molded from a first mold resin and a second skirt portion molded from a second mold resin are provided on a heat dissipating surface of a lead frame. Also, a thinly-molded portion is molded integrally with the second skirt portion from the second mold resin. According to this kind of configuration, adhesion between the thinly-molded portion and lead frame is high, and the semiconductor device with excellent heat dissipation and insulation is obtained.

An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second principal surface, an electronic component disposed on the first principal surface and electrically connected to the metal pattern layer, at least one metal member disposed on the first principal surface and electrically connected to the metal pattern layer, a sealing resin layer disposed on the first principal surface, the electronic component and the at least one metal member, and an insulating layer disposed on the second principal surface. The at least one metal member is thicker than the electronic component. In plan view, the at least one metal member is disposed on an area of the first principal surface, the area including an end of the first principal surface. The at least a part of the metal pattern layer is exposed from the insulating layer.

An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die.

A semiconductor die is attached to a die pad of a leadframe. The semiconductor die attached to the die pad is arranged in a molding cavity between complementary first and second mold portions. Package material is injected into the molding cavity via at least one injection channel provided in one of the complementary first and second mold portions. Air is evacuated from the molding cavity via at least one air venting channel provided in the other of the complementary first and second mold portions. An exit from the at least one air venting channel may be blocked by a retractable stopper during the injection of the package material.

[Problem] An object of the present invention is to provide an electronic part mounting heat-dissipating substrate which enables a circuit for which a power semiconductor in which a large current flows is used to reduce the wiring resistances of a large power operation and improve the heat dissipation.

[Means for Solving] The present invention is an electronic part mounting heat-dissipating substrate which comprises lead frames of wiring pattern shapes formed by conductor plate and an insulating member 130 which is provided between the lead frames 110, wherein a plate surface of a part arrangement surface of said conductor plate and a top surface of said insulating member at a side of said part arrangement surface form one continuous surface, the lead frames have different thicknesses, the thick lead frame 110H is used for a large current signal and the thin lead frame 110L is used for a small current signal, a plate surface of a back surface of the part arrangement surface and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane.

An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a first set of metal lines and a second set of metal lines. The first set of metal lines cross over the second set of metal lines at crossings. The first set of metal lines is separated by a molding compound from the second set of metal line at the crossings. The first set of metal lines is in a same first plane parallel to the semiconductor die. Each of the second set of metal lines include a first portion oriented along the first set of metal lines and disposed in the first plane, and a second portion offset from the first portion. A plurality of electrical connections couple the semiconductor die to the plurality of leads.

A structure comprises a plurality of top pads protruding over a top surface of a package substrate, wherein a top pad comprises a first half-circle portion, a second half-circle portion and a first rectangular portion between the first half-circle portion and the second half-circle portion, a plurality of bottom pads embedded in the package substrate, wherein a bottom pad comprises a third half-circle portion, a fourth half-circle portion and a second rectangular portion between the third half-circle portion and the fourth half-circle portion and a plurality of vias coupled between the top pads and their respective bottom pads.

Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.