The disclosed principles provide for implementing low-cost and fast metallic printing processes into the QFN and other no-leads package assembly flow to selectively print solderable material in areas that would otherwise be susceptible to corrosion and thus pose reliability risks. The problem of copper corrosion and poor BLR performance in no-leads packages because of remaining exposed copper areas after package singulation is solved by employing selective metallic printing processes in the assembly flow to coat all risk-prone areas with solder material. For example, for no-leads packages that are formed using printed leadframes, solder can be deposited through inkjet, screen, stencil, or photonic printing into the grooves which are formed after passivating the packages at the strip level. The singulating occurs through the grooves having solder printed therein, and results in wettable upper and sidewall surfaces of the outer ends of the leadframe for each package.

A method of making semiconductor packages includes providing a first lead frame having a first plurality of semiconductor dies arranged along a first longitudinal axis, each of the first plurality of semiconductor dies having a first number of metal contacts; providing a second lead frame having a second plurality of semiconductor dies arranged along a second longitudinal axis, each of the second plurality of semiconductor dies having a second number of metal contacts, the second number of metal contacts different than the first number of metal contacts; and covering the first plurality of semiconductor dies in a first mold using a common semiconductor die cavity; covering the second plurality of semiconductor dies in a second mold using the common semiconductor die cavity.

A lead frame includes: a lead portion; a plating layer that is provided on a connected area of the lead portion, the connected area being an area connected with a semiconductor element; a recessed portion that is provided around the plating layer on the lead portion; and an oxidized layer that is provided on a surface including the recessed portion of the lead portion.

An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.

The disclosure provides a semiconductor package substrate, a semiconductor package, and a method of manufacturing the semiconductor package substrate. An embodiment of the disclosure provides a semiconductor package substrate including a base substrate including a die pad portion and a lead portion, a metal catalyst layer arranged on the base substrate, and a graphene layer arranged on the metal catalyst layer.

A semiconductor device includes: a semiconductor element; and a first conductor and a second conductor respectively joined to a first surface and a second surface of the semiconductor element via Sn-based solder, in which a Ni-based plated layer is formed on surfaces of the first conductor and the second conductor that oppose the Sn-based solder and on the first surface and the second surface of the semiconductor element, and an interface reaction inhibition layer made of (Cu, Ni).sub.6Sn.sub.5 and having a layer thickness of 1.2 to 4.0 μm is formed at an interface between the Ni-based plated layer and the Sn-based solder.

In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.

A semiconductor package includes a leadframe including a plurality of pre-separated leads on at least opposing sides. There is metal plating on a distal end of the plurality of pre-separated leads including on an outer facing edge. A semiconductor die having bond pads is mounted on the leadframe having the bond pads electrically connected to the plurality of pre-separated leads.

A flexible circuit board and an electronic device including a flexible circuit board are provided. The flexible circuit board may include a substrate having a bending area and a non-bending area, a wiring pattern layer provided on the bending area and the non-bending area, a plating layer provided on the wiring pattern layer and including an open area in an area corresponding to the bending area, and a protective layer that directly contacts one surface of the wiring pattern layer exposed at the open area and a side surface of the plating layer. The protective layer may have a larger thickness than a thickness of the plating layer.

The present disclosure generally relates to a silver sintered molybdenum (SSM) packaging for power semiconductor devices and a method of manufacturing thereof. The SSM packaging comprises a substrate; a MOSFET die comprising a first side and a second side, wherein the first side is bonded to the substrate using nano silver sintering; and at least two leads connected, at a respective first end, to the substrate and, at a respective second end, to the second side of the MOSFET die, wherein nano silver sintering is used to bond the first and second ends of the at least two leads, and wherein each of the substrate and at least two leads is formed of pure molybdenum.