The present invention relates to a resist composition, especially for use in the production of electronic components via electron beam lithography. In addition to the usual base polymeric component (resist polymer), a secondary electron generator is included in resist compositions of the invention in order to promote secondary electron generation. This unique combination of components increases the exposure sensitivity of resists in a controlled fashion which facilitates the effective production of high-resolution patterned substrates (and consequential electronic components), but at much higher write speeds.

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

One embodiment includes partially forming a first through via in a substrate of an interposer, the first through via extending into a first side of the substrate of the interposer. The method also includes bonding a first die to the first side of the substrate of the interposer. The method also includes recessing a second side of the substrate of the interposer to expose the first through via, the first through via protruding from the second side of the substrate of the interposer, where after the recessing, the substrate of the interposer is less than 50 μm thick. The method also includes and forming a first set of conductive bumps on the second side of the substrate of the interposer, at least one of the first set of conductive bumps being electrically coupled to the exposed first through via.

An electrical conductor structure comprises a substrate and an electrical conductor disposed on or in the substrate. The electrical conductor comprises a first layer and a second layer disposed on a side of the first layer opposite the substrate. The first layer comprises a first electrical conductor that forms a non-conductive layer on a surface of the first electrical conductor when exposed to air and the second layer comprising a second electrical conductor that does not form a non-conductive layer on a surface of the second electrical conductor when exposed to air. A component comprises a connection post that is electrically connected to the second layer and the electrical conductor. The first and second layers can be inorganic. The first layer can comprise a metal such as aluminum and the second layer can comprise an electrically conductive metal oxide such as indium tin oxide.

A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.

A semiconductor package device includes a first semiconductor package, a second semiconductor package, and first connection terminals between the first and second semiconductor packages. The first semiconductor package includes a lower redistribution substrate, a semiconductor chip, and an upper redistribution substrate vertically spaced apart from the lower redistribution substrate across the semiconductor chip. The upper redistribution substrate includes a dielectric layer, redistribution patterns vertically stacked in the dielectric layer and each including line and via parts, and bonding pads on uppermost redistribution patterns. The bonding pads are exposed from the dielectric layer and in contact with the first connection terminals. A diameter of each bonding pad decreases in a first direction from a central portion at a top surface of the upper redistribution substrate to an outer portion at the top surface thereof. A thickness of each bonding pad increases in the first direction.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

Provided is a method for manufacturing a semiconductor package, the method including providing a semiconductor chip on a substrate, providing a bonding member between the substrate and the semiconductor chip, and bonding the semiconductor chip on the substrate by irradiating of a laser on the substrate. Here, the bonding member may include a thermosetting resin, a curing agent, and a laser absorbing agent.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.