Disclosed herein are local bridge-last architectures for heterogeneous integration applications and methods for manufacturing the same. The local bridge-last architectures may include a substrate, a first die, a second die, and a material. The substrate may define a cavity. The first and second dies may be connected to the substrate. The material may be attached to the substrate. The material may include a first portion and a second portion. The first portion of the material may be located proximate the first bump and the second portion of the material may be located proximate the second bump.

A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.

A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.

A semiconductor device includes a substrate, an electrical conductor and a passivation layer. The substrate includes a first surface. The electric conductor is over the first surface of the substrate. The passivation layer is over the first surface of the substrate. The passivation layer includes a first part and a second part. In some embodiments, the first part is in contact with an edge of the electrical conductor, the second part is connected to the first part and apart from the edge of the electrical conductor, and the first part of the passivation layer has curved surface.

An imaging element according to the present disclosure is an imaging element flip-chip mounted on a wiring substrate, in which a projection is provided on a side surface of the imaging element such that a bottom surface side of the imaging element projects from a top surface side. Then, in the imaging device according to the present disclosure, the imaging device is flip-chip mounted on the wiring substrate so that a top surface of the imaging element faces the wiring substrate, and an outer periphery of the imaging element on the wiring substrate is sealed with a sealing material. An adhesion site of the sealing material is urged to a side of the projection, so that penetration of a solute and a solvent forming the sealing material may be reduced.

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.

A method of manufacturing a semiconductor package may include providing a substrate having first and second cutting regions respectively provided along first and second side portions opposite to each other and a mounting region between the first and second cutting regions is provided, disposing at least one semiconductor chip on the mounting region, forming a molding member on the substrate, and removing a dummy curl portion and at least portions of dummy runner portions from the molding member. The molding member may include a sealing portion, the dummy curl portion provided outside the second side portion of the substrate, and the plurality of dummy runner portions on the second cutting region to connect the sealing portion and the dummy curl portion. The substrate may include adhesion reducing pads in the second cutting region, which may contact the dummy runner portions respectively.