A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.

A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.

A method and apparatus for soldering a chip (1a) to a substrate (3). A chip carrier (8) is provided between a flash lamp (5) and the substrate (3). The chip (1a) is attached to the chip carrier (8) on a side of the chip carrier (8) facing the substrate (3). A solder material (2) is disposed between the chip (1a) and the substrate (3). The flash lamp (5) generates a light pulse (6) for heating the chip (1a). The heating of the chip (1a) causes the chip (1a) to be released from the chip carrier (8) towards the substrate (3). The solder material (2) is at least partially melted by contact with the heated chip (1a) for attaching the chip (1a) to the substrate (3).

A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section.

The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.

A semiconductor device assembly that includes a semiconductor device positioned over a substrate with a number of electrical interconnections formed between the semiconductor device and the substrate. The surface of the substrate includes a plurality of discrete solder mask standoffs that extend towards the semiconductor device. A thermal compression bonding process is used to melt solder to form the electrical interconnects, which lowers the semiconductor device to contact and be supported by the plurality of discrete solder mask standoffs. The solder mask standoffs permit the application of a higher pressure during the bonding process than using traditional solder masks. The solder mask standoffs may have various polygonal or non-polygonal shapes and may be positioned in pattern to protect sensitive areas of the semiconductor device and/or the substrate. The solder mask standoffs may be an elongated shape that protects areas of the semiconductor device and/or substrate.

A packaged semiconductor device has a plurality of leads. A respective lead is to be welded to an electrical coupling that has a substantially rectangular end section. The end section has a width that is greater than a width of the respective lead. The respective lead is aligned within the width of the end section, such that the respective lead extends in a direction substantially perpendicular to the width of the end section. With the respective lead and the end section aligned, the respective lead is welded to the end section.

Disclosed is a probe bonding device and method. The probe bonding device includes, a second gripper configured to move the probe to a bonding position on the substrate, a laser unit configured to emit a laser beam, a fourth vision device configured to check whether the probe gripped by the second gripper; and a controller configured to control the second gripper and the fourth vision device, wherein the controller controls the fourth vision device to photograph one end of the probe a plurality of numbers of times while sequentially adjusting a height of at least one of the second gripper and the fourth vision device at a predetermined interval to acquire information on a height of the probe based on a plurality of captured images, thereby bonding the probe to an accurate position to enhance bonding quality of the probe and quality of a probe card.

A method and apparatus for soldering a chip (1a) to a substrate (3). A chip carrier (8) is provided between a flash lamp (5) and the substrate (3). The chip (1a) is attached to the chip carrier (8) on a side of the chip carrier (8) facing the substrate (3). A solder material (2) is disposed between the chip (1a) and the substrate (3). The flash lamp (5) generates a light pulse (6) for heating the chip (1a). The heating of the chip (1a) causes the chip (1a) to be released from the chip carrier (8) towards the substrate (3). The solder material (2) is at least partially melted by contact with the heated chip (1a) for attaching the chip (1a) to the substrate (3).

A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.