Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.

A mounting structure, including: a first component that has a first bump; a second component that has a second bump; a mounting component that has a primary mounting surface and a secondary mounting surface; a first solder that connects an electrode on the primary mounting surface and the first bump; a second solder that connects an electrode on the secondary mounting surface and the second bump; and a reinforcing resin that covers a part of the first solder and that is not in contact with the primary mounting surface.

An electronic device and method is disclosed. In one example, the electronic device includes a solderable surface and at least one surface opening arranged in the solderable surface. The electronic device further includes an encapsulation material, encapsulating at least one electronic component of the electronic device, and at least one vent opening arranged in an area of the surface opening and extending through the encapsulation material.

A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.

A semiconductor device includes a semiconductor package equipped with a plurality of electrodes and a mount member which is equipped with a plurality of lands and on which the semiconductor package is mounted. The semiconductor package has the electrodes joined to the lands through solders. One of the electrodes is designed as a position/orientation control electrode for the semiconductor package. One of the lands is designed as a position/orientation control land for the semiconductor package. The position/orientation control land is arranged inside the position/orientation control electrode in a planar view thereof and includes a plurality of first extensions which extend in different radial directions about the center of the semiconductor package. The position/orientation control electrode includes a plurality of second extensions which extend along the first extensions. Each of the first extension has an outer portion which is located outside an outer line of a facing one of the second extensions. The outer portions are arranged to be symmetrical with respect to the center of the semiconductor package.

The present description provides a method for manufacturing electronic components. with wettable flanks. In an example, the method of manufacturing electronic components is for electronic components with wettable flanks from a substrate. A first face of the substrate is covered by connection terminals. The substrate is in which chips are formed. The method includes soldering a metal grid comprising connection pads interconnected by bars to the connection terminals; forming an insulating resin layer on the substrate, wherein the insulating resin layer surrounds the connection pads; separating the chips from one another; and obtaining electronic components with wettable flanks, wherein a lateral part of the connection pads and a part of the insulating resin layer form the wettable flanks of the electronic components.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.

A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.

A package structure includes a substrate, a chip disposed on the substrate, a plurality of spaced-apart connection pillars disposed on the substrate exposed by the chip, and two ends of an extension direction of the connection pillars are a first end and a second end, respectively, the first end being connected with the substrate, and a base board located above the substrate, and a passive component is formed on a side of the base board facing the chip, the passive component being connected with the second end of the plurality of the connection pillars.