A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

An apparatus includes a nozzle including a small die vacuum line disposed on a surface of the nozzle, and a large die vacuum line disposed on the surface and surrounding the small die vacuum line. The nozzle further includes a first die vacuum hole disposed through the surface and the small die vacuum line, and a second die vacuum hole disposed through the surface and the large die vacuum line. The small die vacuum line and the first die vacuum hole are configured to provide a vacuum to a small semiconductor die to be attached to a substrate, and the small die vacuum line, the large die vacuum line, the first die vacuum hole and the second die vacuum hole are configured to provide the vacuum to a large semiconductor die to be attached to the substrate.

An apparatus includes a nozzle including a small die vacuum line disposed on a surface of the nozzle, and a large die vacuum line disposed on the surface and surrounding the small die vacuum line. The nozzle further includes a first die vacuum hole disposed through the surface and the small die vacuum line, and a second die vacuum hole disposed through the surface and the large die vacuum line. The small die vacuum line and the first die vacuum hole are configured to provide a vacuum to a small semiconductor die to be attached to a substrate, and the small die vacuum line, the large die vacuum line, the first die vacuum hole and the second die vacuum hole are configured to provide the vacuum to a large semiconductor die to be attached to the substrate.

A method of fabricating a semiconductor package structure is provided. The method includes applying a plurality of first adhesive portions onto a carrier; applying a second adhesive portion onto the carrier; disposing a plurality of micro pins respectively in the first adhesive portions, such that each of the micro pins has a first portion embedded in a corresponding one of the first adhesive portions and a second portion protruding from said corresponding one of the first adhesive portions; bonding a die to the second adhesive portion; forming a molding compound surrounding the micro pins and the die; and removing the carrier from the molding compound after forming the molding compound.

Electronic devices including a layer of polymeric material and solid semiconductor dies partially embedded in the layer are provided. The dies have first ends projecting away from the first major surface of the layer. The electronic devices can be formed by sinking the first ends of the dies into a major surface of a liner. A flowable polymeric material is filled into the space between the dies and solidified to form the layer of polymeric material. The first ends of the dies are exposed by delaminating the liner from the first ends of the dies. Electrical conductors are provided on the layer to connect the first ends of the dies.

A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

A semiconductor device includes a substrate, a first adhesive layer, a first semiconductor chip, and a second adhesive layer. The first adhesive layer is provided above a first surface of the substrate and includes a plurality of types of resins having different molecular weights and a filler. The first semiconductor chip is provided above the first adhesive layer. The second adhesive layer is provided in at least a part of a first region between the substrate and the first adhesive layer, and the second adhesive layer includes at least one type of resins among the plurality of types of resins having a molecular weight smaller than a molecular weight of other types of resins among the plurality of types of resins, and a filler having a lower concentration than that of the first adhesive layer.

A method of forming an HBT structure includes forming an HBT epitaxial layer structure over a first substrate wafer; performing a first substrate transfer of the HBT epitaxial layer structure and the first substrate wafer onto a second substrate wafer, including inverting the HBT epitaxial layer structure and the first substrate wafer; removing the first substrate wafer; forming a first subcollector metal layer over the HBT epitaxial layer structure; performing a second substrate transfer of the subcollector metal layer and the HBT epitaxial layer structure onto a third substrate wafer with a second subcollector metal layer, including inverting the subcollector metal layer and the epitaxial layer structure; compression bonding the first and second subcollector metal layers to provide a bonded subcollector metal layer; and removing the second substrate wafer. The HBT structure includes the third substrate wafer, the bonded subcollector metal layer, and the HBT epitaxial layer structure.

A method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate lower in rigidity than the first substrate to a first principal surface, on which the first structure is formed, of the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The second substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the second substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.