H01L21/67103

REACTOR SYSTEM AND METHOD FOR FORMING A LAYER COMPRISING INDIUM GALLIUM ZINC OXIDE

Reactor systems and methods for forming a layer comprising indium gallium zinc oxide are disclosed. The layer comprising indium gallium zinc oxide can be formed using one or more reaction chambers of a process module.

Substrate cleaning compositions, substrate cleaning method and substrate treating apparatus

A composition for cleaning a substrate is provided. According to an embodiment, the composition for cleaning the substrate includes an organic solvent having a Hansen solubility parameter of 5 or more to 12 or less for polystyrene latex to the substrate.

Substrate processing apparatus and substrate processing method

A substrate processing apparatus includes a liquid processing module, including a carry-out/in port of a substrate, in which a first liquid processing device and a second liquid processing device provided at a position farther from the carry-out/in port than the first liquid processing device is are provided; and a transfer device configured to carry the substrate out from and into the liquid processing module. The first liquid processing device performs a first liquid processing on the substrate. The second liquid processing device performs a second liquid processing on the substrate before or after the first liquid processing. The transfer device includes a substrate holder configured to be moved back and forth in a first horizontal direction, and carries the non-processed substrate into the first liquid processing device through the carry-out/in port and carries the processed substrate out from the first liquid processing device through the carry-out/in port.

Multi-zone heater model-based control in semiconductor manufacturing

A plurality of heating zones in a substrate support assembly in a chamber is independently controlled. Temperature feedback from a plurality of temperature detectors is provided as a first input to a process control algorithm, which may be a closed-loop algorithm. A second input to the process control algorithm is targeted values of heater temperature for one or more heating zones, as calculated using a model. Targeted values of heater power needed for achieving the targeted values of heater temperature for the one or more heating zones is calculated. Chamber hardware is controlled to match the targeted value of heater temperature that is correlated with the wafer characteristics corresponding to the current optimum values of the one or more process parameters.

Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium

Described herein is a technique capable of improving a uniformity of the characteristics of a film formed on a surface of a substrate by a rotary type apparatus. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber in which a substrate is processed; a substrate support provided in the process chamber and including a plurality of placement parts on which the substrate is placed; a main nozzle provided so as to face a placement part among the plurality of the placement parts and including a first portion where no hole is provided so as to thermally decompose a process gas; and an auxiliary nozzle provided so as to face the placement part and including a second portion where no hole is provided so as to thermally decompose the process gas.

SUBSTRATE PROCESSING DEVICE HAVING HEAT HOLE

A substrate processing device according to an embodiment of the present invention includes a disk part disposed in a chamber in which a heating means is provided, and a pocket part installed on one surface of the disk part and on which a substrate is seated. A heat hole through which heat generated by the heating means passes may be formed on an installation surface of the disk part on which the pocket part is installed, or a gear hole through which the heat of the heating means passes may be formed in a pocket gear facing the disk part.

COLD CONDUIT INSULATION DEVICE
20220397354 · 2022-12-15 · ·

A thermal insulation structure includes an insulation layer having a first surface proximate a cooling device and a second surface opposing the first surface. A heater is disposed proximate the second surface, and a protective layer is disposed proximate the heater layer such that the heater layer is disposed between the insulation layer and the protective layer. The heater layer is configured to reduce frost or ice buildup on an exterior surface of the insulation layer.

FOCUS RING PLACEMENT TABLE
20220399190 · 2022-12-15 · ·

A focus ring placement table includes an annular ceramic heater on which a focus ring is placed, a metal base, an adhesive element bonding the metal base and the ceramic heater, an inner-peripheral-side protective element disposed between the metal base and the ceramic heater and bonded to an inner peripheral portion of the adhesive element, and an outer-peripheral-side protective element disposed between the metal base and the ceramic heater and bonded to an outer peripheral portion of the adhesive element. A coefficient of thermal expansion of the adhesive element is equal to or smaller than a coefficient of thermal expansion of the inner-peripheral-side protective element and is equal to or greater than a coefficient of thermal expansion of the outer-peripheral-side protective element.

MEMBER FOR SEMICONDUCTOR MANUFACTURING APPARATUS
20220400539 · 2022-12-15 · ·

A member for a semiconductor manufacturing apparatus includes a disk-shaped or annular ceramic heater, a metal base, an adhesive element bonding the metal base and the ceramic heater, an adhesive protective element disposed between the ceramic heater and the metal base to extend along a periphery of the adhesive element, and an anti-adhesion layer disposed between the adhesive element and the protective element, the anti-adhesion layer preventing adhesion between the adhesive element and the protective element.

WAFER PLACEMENT TABLE
20220399223 · 2022-12-15 · ·

A wafer placement table includes a ceramic substrate that has a wafer placement surface, a first electrode that is embedded in the ceramic substrate, a first power supply terminal that is inserted from a surface of the ceramic substrate opposite the wafer placement surface toward the first electrode, a first joint that joins the first electrode and the first power supply terminal to each other and a second electrode that is disposed between the wafer placement surface and the first electrode in the ceramic substrate. A linear portion that extends in the ceramic substrate from a position on the first electrode opposite the first joint to the wafer placement surface is composed of material of the ceramic substrate.