H01L21/68721

METHOD AND APPARATUS FOR PLASMA DICING A SEMI-CONDUCTOR WAFER

The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

FLAT BOTTOM SHADOW RING

In some examples, a flat Bottom Shadow Ring (fBSR) is provided for processing a substrate in a processing chamber. An example fBSR comprises an overhang for covering an edge of the substrate in the processing chamber. The overhang includes a fiat zone that extends radially outward over the outer edge of the substrate.

SUBSTRATE PROCESSING SYSTEM AND TRANSFER METHOD

A substrate processing system includes a vacuum transfer module; a plasma process module; a transfer robot in the vacuum transfer module; a stage in the plasma process module; a first ring disposed on the stage and a second ring disposed on the first ring to surround a substrate that is placed on the stage, the second ring having an inner diameter smaller than an inner diameter of the first ring; actuators to move support pins vertically to raise the first and the second rings and a transfer jig; and a controller configured to selectively execute a simultaneous transfer mode in which the transfer robot is caused to simultaneously transfer the first ring and the second ring and a sole transfer mode in which the transfer robot is caused to transfer only the second ring.

Manufacturing process of element chip using laser grooving and plasma-etching

A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

Apparatus to reduce polymers deposition

Implementations of the present disclosure provide a process kit for an electrostatic chuck. In one implementation, a substrate support assembly is provided. The substrate support assembly includes an electrostatic chuck having a first recess formed in an upper portion of the electrostatic chuck. A process kit surrounds the electrostatic chuck. The process kit includes an inner ring and an outer ring disposed radially outward of the inner ring. The outer ring includes a second recess formed in an upper portion of the upper ring. The inner ring is positioned within and is supported by the first recess and the second recess. An upper surface of the inner ring and an upper surface of the outer ring are co-planar.

Lift thimble system, reaction chamber, and semiconductor processing equipment

The present disclosure discloses a lift thimble system, a reaction chamber, and semiconductor processing equipment, including a wafer thimble device configured to lift a wafer from a base by rising or drop the wafer onto the base by descending, and a focus ring thimble device configured to lift a focus ring from an initial position of the focus ring by rising to cause an inner ring area of an upper surface of the focus ring to lift an edge area of the wafer, or cause the focus ring to return to the initial position by descending. The technical solutions of the system, the reaction chamber, and the equipment of the present disclosure improve maintenance efficiency of an abnormal situation, and double the service lifetime of the focus ring. Moreover, the technical solutions may further realize replacement of the focus ring without damaging reaction chamber vacuum to improve efficiency.

SHADOW RING LIFT TO IMPROVE WAFER EDGE PERFORMANCE
20230002894 · 2023-01-05 ·

A method and apparatus for processing a substrate are described herein. The methods and apparatus described enable the raising and lowering of a shadow ring within a process chamber either simultaneously with or separately from a plurality of substrate lift pins. The shadow ring is raised and lowered using a shadow ring lift assembly and may be raised to a pre-determined height above the substrate during a radical treatment operation. The shadow ring lift assembly may also raise and lower the plurality of substrate lift pins to enable both the shadow ring and the substrate lift pins to be raised to a transfer position when the substrate is being transferred into or out of the process chamber.

Semiconductor wafer dicing process

A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies. Scribe lines are formed within a polymer coating to expose regions of wafer to form a pre-processed product. The pre-processed product within the chamber is plasma etched to remove the exposed regions of the wafer to separate the individual dies and form a processed product. A frame cover is then removed and the processed product, wafer frame and adhesive tape are exposed to an oxygen plasma within the chamber to partially remove an outermost region of the polymer coating, which is most heavily contaminated with fluorine, to leave a residual polymer coating on the individual dies and form a post-processed product. The residual polymer coating on the individual dies of the post-processed product is then removed.

Wafer carrier and method

A wafer carrier includes a pocket sized and shaped to accommodate a wafer, the pocket having a base and a substantially circular perimeter, and a removable orientation marker, the removable orientation marker comprising an outer surface and an inner surface, the outer surface having an arcuate form sized and shaped to mate with the substantially circular perimeter of the pocket, and the inner surface comprising a flat face, wherein the removable orientation marker further comprises a notch at a first end of the flat face.

System and method for edge ring wear compensation

A controller for adjusting a height of an edge ring in a substrate processing system includes an edge ring wear calculation module configured to receive at least one input indicative of one or more erosion rates of the edge ring, calculate at least one erosion rate of the edge ring based on the at least one input, and calculate an amount of erosion of the edge ring based on the at least one erosion rate. An actuator control module is configured to adjust the height of the edge ring based on the amount of erosion as calculated by the edge ring wear calculation module.