An integrated circuit (IC) includes a first capacitor, a second capacitor, and functional circuitry configured together with the capacitors for realizing at least one circuit function in a semiconductor surface layer on a substrate. The capacitors include a top plate over a LOCal Oxidation of Silicon (LOCOS) oxide, wherein a thickness of the LOCOS oxide for the second capacitor is thicker than a thickness of the LOCOS oxide for the first capacitor. There is a contact for the top plate and a contact for a bottom plate for the first and second capacitors.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

Embodiments of the invention are directed to a transistor that includes a source or drain (S/D) region having an S/D formation assistance region, wherein the S/D formation assistance region includes a top surface, sidewalls, and a bottom surface. The S/D formation assistance region is at least partially within a portion of a substrate. An S/D isolation region is formed around the sidewalls and the bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

A lateral double diffused metal oxide semiconductor (LDMOS) transistor and a semiconductor can reduce the size of the entire power block and can decrease costs by preventing formation of an edge termination region between adjacent device tips or ends along a width direction when the corresponding LDMOS transistor cell has a limited width and the LDMOS transistor is a multi-finger LDMOS transistor.

Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having an S/D formation assistance region at least partially within a portion of a substrate. An S/D isolation region is formed around sidewalls and a bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.

Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.

A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a III-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.

An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.