A structure and a method for fabricating interconnections for an integrated circuit device are described. The method forms a metal interconnection pattern having a first barrier layer and a copper layer in a set of trenches in a first dielectric layer over a substrate. In a selected area, the first dielectric layer is removed to so that the first barrier layer can be removed at the exposed vertical surfaces. A thin second barrier layer is deposited over the exposed vertical surfaces of the first copper layer. A structure includes a first feature formed in a first dielectric layer which has a first barrier layer disposed on vertical surfaces of the first dielectric layer and surrounds opposing vertical surfaces and a bottom surface of a copper layer. The structure also includes a second feature formed in a second dielectric layer which has a second barrier layer disposed on vertical surfaces of the second dielectric layer and two vertical surfaces of the copper layer and a bottom surface of the first copper layer is disposed over the first barrier layer.

A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.

The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.

In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.

The present invention provides, in polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, means that is capable of improving a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials. The present invention relates to a polishing composition used for polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, the polishing composition containing: organic acid-immobilized silica; a dispersing medium; a selection ratio improver that improves a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials; and an acid, in which the selection ratio improver is organopolysiloxane having a hydrophilic group.

An integrated circuit includes a base comprising an insulating dielectric. A plurality of conductive lines extends vertically above the base in a spaced-apart arrangement, the plurality including a first conductive line and a second conductive line adjacent to the first conductive line. A void is between the first and second conductive lines. A cap of insulating material is located above the void and defines an upper boundary of the void such that the void is further located between the base and the cap of insulating material. In some embodiments, one or more vias contacts an upper end of one or more of the conductive lines.

A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.