A semiconductor device includes a substrate, a first metal layer, a dielectric layer, and a second metal layer. The substrate includes a dense region and an isolation region. The first metal layer is disposed over the substrate and includes a first metal pattern and a second metal pattern. The first metal pattern is located in the dense region. There is at least one slot in the first metal pattern. The second metal pattern is located in the isolation region. The dielectric layer is disposed on the first metal layer. The second metal layer is disposed on the dielectric layer.

A method of fabricating fully self-aligned vias includes performing a first deposition process, forming a second dielectric layer, performing a first chemical mechanical polishing (CMP) process, performing a selective removal plasma process to form second vias, performing a second deposition process to deposit an etch stop layer in the second vias, performing a third deposition process, forming a third dielectric layer, performing a second CMP process, performing a first lithography-and-etch process to form third vias in the third dielectric layer, performing a fourth deposition process to form a second metal layer in the third vias, performing a fourth CMP process, performing a fifth deposition process to form a third metal layer of third metal, performing a sixth deposition process to form a second hardmask, performing a second lithography-and-etch process, performing an over etch, performing a seventh deposition process, forming a fourth dielectric layer, performing a fifth CMP process.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

A method includes providing a substrate, a dielectric layer over the substrate, and metallic features over the dielectric layer; and forming an organic blocking layer (OBL) over the dielectric layer and between lower portions of the metallic features. The OBL covers sidewall surfaces of the lower portions, but not upper portions, of the metallic features. The method further includes depositing a dielectric barrier layer over top surfaces of the metallic features and over the sidewall surfaces of the upper portions of the metallic features, wherein at least a portion of a top surface of the OBL is not covered by the dielectric barrier layer; forming an inter-metal dielectric (IMD) layer between the metallic features and above the OBL; and removing the OBL, leaving an air gap above the dielectric layer, below the dielectric barrier layer and the IMD layer, and laterally between the lower portions of the metallic features.

In an aspect, a system on a chip (SOC) includes a plurality of function blocks, including a first function block and a second function block, co-located on the SOC. The SOC includes a first metal layer, a first dielectric layer located on top of the first metal layer, and a first via located in the first dielectric layer and used in the first function block. The SOC includes a second via located in the first dielectric layer and used in the second function block and a second metal layer located on the first dielectric layer. The second metal layer comprises a first set of connections used in the first function block and a second set of connections used in the second function block. The first set of connections is different from the second set of connections. The SOC includes a second dielectric layer located on the first dielectric layer.

Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

To provide modified colloidal silica capable of improving the stability of the polishing speed with time when used as abrasive grains in a polishing composition for polishing a polishing object that contains a material to which charged modified colloidal silica easily adheres, such as a SiN wafer, and to provide a method for producing the modified colloidal silica.

Modified colloidal silica, being obtained by modifying raw colloidal silica, wherein

the raw colloidal silica has a number distribution ratio of 10% or less of microparticles having a particle size of 40% or less relative to a volume average particle size based on Heywood diameter (equivalent circle diameter) as determined by image analysis using a scanning electron microscope.

Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO.sub.2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.