The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming an insulating layer above the substrate; forming a first opening in the insulating layer; conformally forming a first framework layer in the first opening; forming an energy-removable layer on the first framework layer and filling the first opening; forming a second opening along the energy-removable layer and the first framework layer; conformally forming a second framework layer in the second opening; forming a top contact on the second framework layer and filling the second opening and forming a top conductive layer on the top contact; and performing an energy treatment to transform the energy-removable layer into porous insulating layers on two sides of the top contact.

A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes forming a fin-shaped structure extending from a front side of a substrate, recessing a source region of the fin-shaped structure to form a source opening, forming a semiconductor plug under the source opening, exposing the semiconductor plug from a back side of the substrate, selectively removing a first portion of the substrate without removing a second portion of the substrate adjacent to the semiconductor plug, forming a backside dielectric layer over a bottom surface of the workpiece, replacing the semiconductor plug with a backside contact, and selectively removing the second portion of the substrate to form a gap between the backside dielectric layer and the backside contact. By forming the gap, a parasitic capacitance between the backside contact and an adjacent gate structure may be advantageously reduced.

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include a barrier member extending vertically from the bond pad toward the semiconductor substrate and configured to inhibit crack propagation through the insulating material.

In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

An air gap forming method of forming an air gap in a gap structure having an upper surface, a lower surface, and a sidewall connecting the upper and lower surface, includes: repeatedly performing a selective deposition cycle, wherein the selective deposition cycle includes supplying a deposition inhibitor onto a substrate including the gap structure; and selectively forming a material layer on the upper surface compared to the sidewall.

A method may include providing an array of patterned features on a substrate, the array of patterned features characterized by a spacing. The method may include directing a sputtering species in a first exposure to the array of patterned features, wherein an upper portion of a patterned feature of the array of patterned features forms a protrusion, extending towards an adjacent patterned feature, of the array of patterned features. The method may also include directing a depositing species in a second exposure to the array of patterned features, wherein an array of voids is formed between adjacent patterned features.

A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Methods for forming conductive lines and integrated chips include forming a mandrel on an etch stop layer. First spacers are formed on sidewalls of the mandrel. The mandrel is etched away. Conductive lines are formed on sidewalls of the first spacers. The first spacers are etched away. Dielectric spacers are formed between the conductive lines.

A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.