In a method of manufacturing a semiconductor device, a source/drain structure is formed over a substrate, a first interlayer dielectric (ILD) layer including one or more dielectric layers is formed over the source/drain structure, a first opening is formed in the first ILD layer to at least partially expose the source/drain structure, a sacrificial layer is formed on an inner wall of the first opening, a first insulating layer is formed on the sacrificial layer, a conductive layer is formed on the first insulating layer so as to form a source/drain contact in contact with the source/drain structure, the sacrificial layer is removed to form a space between the first insulating layer and the first ILD layer, and a second insulating layer is formed over the source/drain contact and the first ILD layer to cap an upper opening of the space, thereby forming an air gap.

A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.

An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

A memory device includes a substrate, a buried word line, a connecting structure, an air gap, and a first dielectric layer. The buried word line is disposed in the substrate. The connecting structure is disposed on the buried word line. The air gap is disposed on the buried word line and is adjacent to the connecting structure. The first dielectric layer is disposed on the connecting structure and the air gap, wherein the buried word line, the connecting structure, and the first dielectric layer are disposed in the first direction, which is substantially perpendicular to the top surface of the substrate.

A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.

A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.

A method of forming a semiconductor structure and a semiconductor structure are provided. The method of forming the semiconductor structure includes: providing a base, where the base includes a first dielectric layer and pads arranged at intervals in the first dielectric layer; forming a dielectric structure, where the dielectric structure exposes the pad and part of the first dielectric layer; forming an insulating structure, where the insulating structure is formed on a sidewall of the dielectric structure, the insulating structure covers a first partial sidewall of the dielectric structure, and an air gap is formed between a second partial sidewall of the dielectric structure and the insulating structure; and forming a conductive structure, where the conductive structure covers an exposed pad and an outer sidewall surface of the insulating structure.

A method of fabricating a semiconductor device including a two-dimensional material layer defining an air-gap, and the semiconductor device therefrom are provided. The method of fabricating a semiconductor device, includes forming a structure on a substrate, wherein the structure has an opening; loading the substrate into a process chamber; forming at least one two-dimensional material layer on an upper surface of the structure so as to overlie the opening and form an air-gap, wherein an upper portion of the air-gap is defined by the at least one two-dimensional material layer; and unloading the substrate from the process chamber.