A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

An integrated circuit structure comprises one or more first level interconnects (FLIs) embedded in an underfill (UF) over a substrate. An etch stop layer is over the FLIs. A passivation layer is over the etch stop layer and a plurality of vias are through the passivation layer. A plurality of contacts are on the passivation layer in contact with the vias to connect with the FLI. A plurality of topological crack stop (TCS) features are formed in the passivation layer and on a top surface of the etch stop layer.

A method comprises forming a gate structure over a substrate; forming a gate helmet to cap the gate structure; forming a source/drain contact on the substrate; depositing a contact etch stop layer (CESL) over the gate helmet and the source/drain contacts, and an interlayer dielectric (ILD) layer over the CESL; performing a first etching process to form a gate contact opening extending through the ILD layer, the CESL and the gate helmet to the gate structure; forming a metal cap in the gate contact opening; with the metal cap in the gate contact opening, performing a second etching process to form a source/drain via opening extending through the ILD layer, the CESL to the source/drain contact; and after forming the source/drain via opening, forming a gate contact over the metal cap and a source/drain via over the source/drain contact.

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adj acent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

A semiconductor chip includes; an intermetal dielectric (IMD) layer on a substrate, an uppermost insulation layer on the IMD layer, the uppermost insulation layer having a dielectric constant different from a dielectric constant of the IMD layer, a metal wiring in the IMD layer, the metal wiring including a via contact and a metal pattern, a metal pad in the uppermost insulation layer, the metal pad being electrically connected to the metal wiring, and a bump pad on the metal pad. An interface portion between the IMD layer and the uppermost insulation layer is disposed at a height of a portion between an upper surface and a lower surface of an uppermost metal pattern in the IMD layer.

Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.