Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.

Exemplary methods of semiconductor processing may include forming a layer of carbon-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The substrate may include an exposed region of a first dielectric material and an exposed region of a metal-containing material. The layer of carbon-containing material may be selectively formed over the exposed region of the metal-containing material. Forming the layer of carbon-containing material may include one or more cycles of providing a first molecular species that selectively couples with the metal-containing material. Forming the layer of carbon-containing material may include providing a second molecular species that selectively couples with the first molecular species. The methods may include selectively depositing a second dielectric material on the exposed region of the first dielectric material.

An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.

A method for manufacturing a semiconductor device includes depositing a first hard mask layer and a first dielectric layer over a substrate, forming a patterned layer over the first dielectric layer, forming a second hard mask layer over the patterned layer, patterning the second hard mask layer to remove first horizontal portions of the second hard mask layer and leave second portions of the second hard mask layer along sidewalls of the patterned layer, etching a trench in the first dielectric layer using the second portions of the second hard mask layer and the patterned layer as an etching mask, depositing a first gap-filling material in the trench and patterning the first hard mask layer using the first gap-filling material, the patterned layer, and the second portions of the second hard mask layer as a mask.

A semiconductor device and method of manufacture which utilize isolation structures between semiconductor regions is provided. In embodiments different isolation structures are formed between different fins in different regions with different spacings. Some of the isolation structures are formed using flowable processes. The use of such isolation structures helps to prevent damage while also allowing for a reduction in spacing between different fins of the devices.

An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatus includes a first conductive contact; a second conductive contact; levels of conductive materials stacked over one another and located over the first and second conductive contacts; levels of dielectric materials interleaved with the levels of the conductive materials, the levels of conductive materials and the levels of dielectric materials formed a stack of materials; a first conductive structure located on a first side of the stack of materials and contacting the first conductive contact and a first level of conductive material of the levels of conductive materials; and a second conductive structure located on a second side of the stack of materials and contacting the second conductive contact and a second level of conductive material of the levels of conductive materials.

An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.

A multiple-layer method for forming material within a gap on a surface of a substrate is disclosed. An exemplary method includes forming a layer of first material overlying the substrate and forming a layer of second (e.g., initially flowable) material within a region of the first material to thereby at least partially fill the gap with material in a seamless and/or void less manner.

A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 μm or more.