In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

Embodiments of this application provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: a first substrate is provided; the back surface of the first substrate is etched to form a trench; a conductive layer is formed in the trench; a first conductive column that extends into the trench is formed at a back surface of the first substrate; a device layer is formed at a front surface of the first substrate, and the device layer includes a storage array and a contact structure; and a second conductive column that penetrates through the device layer and extends into the first substrate is formed; the first conductive column is electrically connected with the second conductive column through the conductive layer.

A method for processing a semiconductor structure and a method for forming a word line structure are provided. The method for processing the semiconductor structure includes: providing a semiconductor structure including a groove and a metal layer located in the groove, where an edge position of a top surface of the metal layer is higher than a center position of the top surface of the metal layer; enabling the semiconductor structure to be in a rotating state; and performing at least one metal surface planarization process on the semiconductor structure, so that the top surface of the metal layer after being processed is more planar than the top surface of the metal layer before being processed. Each of the at least one metal surface planarization process includes: etching the top surface of the metal layer by a first reagent; and cleaning the semiconductor structure by a second reagent.

Embodiments of methods and associated apparatus for filling a feature in a substrate are provided herein. In some embodiments, a method of filling a feature in a substrate includes: depositing a seed layer of tungsten nitride in the feature via a physical vapor deposition (PVD) process; depositing a liner layer of tungsten on the seed layer of tungsten nitride in the feature via a PVD process; and subsequently filling the feature with a tungsten bulk fill via a chemical vapor deposition (CVD) process.

An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.

The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

The present invention relates to a metal interconnect structure containing no barrier metal and a method of manufacturing the metal interconnect structure. The method includes: filling at least a first interconnect trench with an intermetallic compound by depositing the intermetallic compound on an insulating layer having the first interconnect trench and a second interconnect trench formed in the insulating layer, the second interconnect trench being wider than the first interconnect trench; performing a planarization process of polishing the intermetallic compound until the insulating layer is exposed; and then performing a height adjustment process of polishing the intermetallic compound and the insulating layer until a height of the intermetallic compound in the first interconnect trench reaches a predetermined height.

During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.

The present application discloses method for fabricating a conductive feature and a method for fabricating a semiconductor device. The method includes providing a substrate; forming a recess in the substrate; conformally forming a first nucleation layer in the recess; performing a post-treatment to the first nucleation layer; and forming a first bulk layer on the first nucleation layer to fill the recess. The first nucleation layer and the first bulk layer configure the conductive feature. The first nucleation layer and the first bulk layer include tungsten. The post-treatment includes a borane-containing reducing agent.

A method of forming a cap layer for sealing an air gap is provided. The method includes forming a line feature over a substrate, forming a contact etch stop layer (CESL) on a sidewall of the line feature, forming a sacrificial layer on a sidewall of the CESL, forming a liner layer on a sidewall of the sacrificial layer, removing the sacrificial layer to form an air gap which is bordered at the CESL and the liner layer and which is adjacent to the line feature, etching back upper ends of the CESL and the liner layer to widen an opening of the air gap, and forming a cap layer to seal the opening of the air gap thus widened.