An etch stop layer is located on top of a first dielectric layer. A conductive line is located on top of the etch stop layer. A second dielectric layer is located above the first dielectric layer. The second dialect layer is in contact with the first dielectric layer.

A substrate processing method includes: a carry-in step of carrying a substrate having a silicon-containing film on a surface of the substrate into a processing container; a first step of forming an adsorption layer by supplying an oxygen-containing gas into the processing container and causing the oxygen-containing gas to be adsorbed on a surface of the silicon-containing film; a second step of forming a silicon oxide layer by supplying an argon-containing gas into the processing container and causing the adsorption layer and the surface of the silicon-containing film to react with each other with plasma of the argon-containing gas; and a third step of forming a graphene film on the silicon oxide layer by supplying a carbon-containing gas into the processing container with plasma of the carbon-containing gas.

A method of manufacturing a semiconductor device includes forming a first through via surrounded by a liner in a first semiconductor substrate, first-recessing the semiconductor substrate to expose a first portion of the liner covering an end portion of the first through via, and forming a first diffusion barrier layer covering the first-recessed first semiconductor substrate and exposing a second portion of the liner. The method also includes removing the second portion of the liner and second-recessing the first diffusion barrier layer. The method further includes forming a second diffusion barrier layer that covers the second-recessed first diffusion barrier layer and a top portion of the liner from which the second portion is removed and exposes a top surface of the end portion of the first through via.

A printed structure includes a substrate comprising a substrate surface, a substrate circuit disposed in or on in a circuit area of the substrate surface, a substrate post protruding from the substrate surface exterior to the circuit area, and a component having a component top side and a component bottom side opposite the component top side. The component bottom side can be disposed on the substrate post and adhered to the substrate surface forming an air gap between the component bottom side and the substrate circuit. The substrate post can comprise a substrate post material that is a cured adhesive. Some embodiments comprise a substrate electrode and the component comprises an electrically conductive connection post extending from the component bottom side toward the substrate in electrical contact with the substrate electrode.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.

An electronic fuse (e-fuse) module may be formed in an integrated circuit device. The e-fuse module may include a pair of metal e-fuse terminals (e.g., copper terminals) and an e-fuse element formed directly on the metal e-fuse terminals to define a conductive path between the pair of metal e-fuse terminals through the e-fuse element. The metal e-fuse terminals may be formed in a metal interconnect layer, along with various interconnect elements of the integrated circuit device. The e-fuse element may be formed by depositing and patterning a diffusion barrier layer over the metal e-fuse terminals and interconnect elements formed in the metal interconnect layer. The e-fuse element may be formed from a material that provides a barrier against metal diffusion (e.g., copper diffusion) from each of the metal e-fuse terminals and interconnect elements. For example, the e-fuse element may be formed from titanium tungsten (TiW) or titanium tungsten nitride (TiW.sub.2N).

A semiconductor device includes a first conductive layer including a first metal, a second conductive layer electrically connected to the first conductive layer and including a second metal, and an interconnection structure common to a connection portion of the first and second conductive layers. The interconnection structure may include a seed layer on the first conductive layer that includes graphene, and a metal migration barrier layer on the seed layer that includes MXene.

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.