Cobalt-containing compounds, their synthesis, and their use for the deposition of cobalt containing films are disclosed. The disclosed cobalt-containing compounds have one of the following formulae: wherein each of R.sup.1, R.sup.2, R.sup.3, R.sup.4 and R.sup.5 is independently selected from Hydrogen; halogen; linear, cyclic or branched hydrocarbons; primary amino ligands (—NHR); or secondary amino ligands (—NRR′), with R and R′ independently being H or a linear, cyclic or branched hydrocarbon, provided at least one of R.sup.1, R.sup.2, or R.sup.3 in Formula I and R.sup.4 or R.sup.5 in Formula II is an amino ligand. ##STR00001##

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer, and a conductive structure. The stack structure includes a plurality of conductive layers and a plurality of insulating layers stacked interlacedly. The etching stop layer is formed on a sidewall of the stack structure. An energy gap of the etching stop layer is larger than 6 eV. The conductive structure is electrically connected to at least one of the conductive layers.

Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW.sub.2O.sub.8) or hafnium tungstate (HfW.sub.2O.sub.8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages. Other embodiments which can employ techniques described herein will be apparent in light of this disclosure.

Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring layer on a wafer includes the following steps. A copper layer is formed on the wafer. A patterned hardmask is formed on the copper layer. The copper layer is subtractively patterned using the patterned hardmask to form a plurality of first copper lines. Spacers are formed on opposite sides of the first copper lines. A planarizing dielectric material is deposited onto the wafer, filling spaces between the first copper lines. One or more trenches are etched in the planarizing dielectric material. The trenches are filled with copper to form a plurality of second copper lines that are self-aligned with the first copper lines. An electronic device is also provided.

Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

The present disclosure provides a semiconductor device with a copper-manganese liner and a method for preparing the semiconductor device. The semiconductor device includes a first well region and a second well region disposed in a semiconductor substrate. The semiconductor device also includes a first dielectric layer disposed over the semiconductor substrate and covering the first well region and the second well region, and a gate structure disposed over the first dielectric layer and between the first well region and the second well region. The semiconductor device further includes a conductive structure disposed over and separated from the first well region by a portion of the first dielectric layer. The conductive feature includes a barrier layer and a conductive plug disposed over the barrier layer, and the barrier layer is made of copper-manganese (CuMn). The first well region, the conductive structure and the portion of the first dielectric layer form an anti-fuse structure.

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

The present invention aims to provide a method for producing a semiconductor device, the method being capable of achieving high reliability by suppressing voids. The present invention also aims to provide a flip-chip mounting adhesive for use in the method for producing a semiconductor device. The present invention relates to a method for producing a semiconductor device, including: step 1 of positioning a semiconductor chip on a substrate via an adhesive, the semiconductor chip including bump electrodes each having an end made of solder; step 2 of heating the semiconductor chip at a temperature of the melting point of the solder or higher to solder and bond the bump electrodes of the semiconductor chip to an electrode portion of the substrate, and concurrently to temporarily attach the adhesive; and step 3 of removing voids by heating the adhesive under a pressurized atmosphere, wherein the adhesive has an activation energy ΔE of 100 kJ/mol or less, a reaction rate of 20% or less at 2 seconds at 260° C., and a reaction rate of 40% or less at 4 seconds at 260° C., as determined by differential scanning calorimetry and Ozawa method.

A method of depositing a film is provided. In the method, one operation of a unit of film deposition process is performed by carrying a substrate into a processing chamber, by depositing a nitride film on the substrate, and by carrying the substrate out of the processing chamber after finishing depositing the nitride film on the substrate. The one operation is repeated a predetermined plurality of number of times continuously to deposit the nitride film on a plurality of substrates continuously. After that, an inside of the processing chamber is oxidized by supplying an oxidation gas into the processing chamber.

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.