An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Provided are semiconductor and a method for manufacturing semiconductor. The semiconductor structure includes: a substrate and a gate located on the substrate, a source is formed in the substrate on one side of the gate, and a drain is formed in the substrate on another side of the gate; a dielectric layer covering a surface of the gate; a contact structure passing through the dielectric layer and electrically connected to the source or the drain, the contact structure including a stack of a first contact layer and a second contact layer, and in a direction from the source to the drain, a width of the second contact layer being greater than a width of the first contact layer; and an electrical connection layer located at a top surface of the dielectric layer and in contact with part of a top surface of the second contact layer.

A method of fabricating a semiconductor device is disclosed. The method may include forming an etch-target layer, a mask layer, a blocking layer, and a photoresist layer, which are sequentially stacked on a substrate; forming a photoresist pattern, the forming the photoresist pattern including irradiating the photoresist layer with extreme ultraviolet (EUV) light; forming a mask layer, the forming the mask layer including etching the mask layer using the photoresist pattern as an etch mask; and forming a target pattern, the forming the target pattern including etching the etch-target layer using the mask pattern as an etch mask. The photoresist layer may include an organic metal oxide. The blocking layer may be a non-polar layer and may limit and/or prevent a metallic element in the photoresist layer from infiltrating into the mask layer.

A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface, and forming a mask by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer. The mask may be formed over the plurality of patterning structures without being formed along the second sidewall. The method may further include selectively forming a metal layer along the second sidewall of each of the plurality of patterning structures.

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a second conductive feature disposed over the first conductive feature. The second conductive feature includes a first sidewall, a first bottom, and a first angle between the first sidewall and the first bottom. The structure further includes a third conductive feature disposed over the dielectric layer and adjacent the second conductive feature. The third conductive feature includes a second sidewall, a second bottom, and a second angle between the second sidewall and the second bottom, the second angle is substantially different from the first angle, and the second and third conductive features are partially overlapping in an axis substantially parallel to a major surface of the substrate.

The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

The present application discloses a method for fabricating a semiconductor device. The method includes: providing a substrate including a plurality of first regions and second regions; forming a plurality of bit line contacts over the first regions of the substrate; forming a plurality of bit lines respectively over the plurality of bit line contacts; forming a plurality of capacitor contacts respectively over the second regions of the substrate; forming a plurality of capacitor plugs respectively over the plurality of capacitor contacts; forming a plurality of first spacers respectively over a plurality of protruding portions of the plurality of capacitor plugs, wherein a width of the first spacer is larger than a width of the capacitor plug; and forming a plurality of capacitor structures over the plurality of first spacers; wherein at least one of the plurality of bit lines is an undulating stripe extending between two adjacent capacitor contacts.

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.