An interconnect or memory structure is provided that includes a first electrically conductive structure having a concave upper surface embedded in a first interconnect dielectric material layer. A first metal-containing cap contacts the concave upper surface of the first electrically conductive structure. The first metal-containing cap has a topmost surface that is coplanar with a topmost surface of the first interconnect dielectric material layer. A second metal-containing cap having a planar bottommost surface contacts the topmost surface of the first metal-containing cap. A metal-containing structure having a planar bottommost surface contacts a planar topmost surface of the second metal-containing cap. A second electrically conductive structure contacts a planar topmost surface of the metal-containing structure, and a second interconnect dielectric material layer is present on the first interconnect dielectric material layer and is located laterally adjacent to second metal-containing cap, the metal-containing structure, and the second electrically conductive structure.

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Techniques are provided for detecting copy number variations. Each sequence read of a set of sequence reads is aligned with a portion of a reference sequence. A coverage vector is generated that includes a plurality of elements, each element in the plurality of elements indicating a number of the set of sequence reads that were aligned to a particular position within the reference sequence. A normalization vector is accessed that was generated based on performance of a component analysis on a set of other coverage vectors corresponding to a set of other subjects. An adjusted coverage vector is generated using the coverage vector and normalization vector. One or more subject-specific normalization values are generated based on the coverage vector. One or more copy number variations are identified that corresponding to the sample using the adjusted coverage vector and the subject-specific normalization values.

An integrated circuit package may be fabricated with a universal dummy device, instead of utilizing a dummy device that matches the bump layer of an electronic substrate of the integrated circuit package. In one embodiment, the universal dummy device may comprise a device substrate having an attachment surface and a metallization layer on the attachment surface, wherein the metallization layer is utilized to form a connection with the electronic substrate of the integrated circuit package. In a specific embodiment, the metallization layer may be a single structure extending across the entire attachment surface. In another embodiment, the metallization layer may be patterned to enable gap control between the universal dummy device and the electronic substrate.

A method for forming an electrical connection structure is provided. The method includes forming a first metal material in an opening of a dielectric layer. The first metal material includes a plurality of grains. The method also includes forming a second metal material over the first metal material. The method also includes annealing the second metal material so that the second metal material diffuses along grain boundaries of the grains of the first metal material. The method also includes removing the second metal material from the upper surface of the first metal material.

A method for manufacturing a semiconductor device (10) includes, in the following order: forming a first insulating film (14) on a semiconductor substrate (12); forming, on the first insulating film (14), wiring in which at least the uppermost layer is made of Au (16); implanting ions, which do not impair insulating properties even when implanted into the insulating film (14), into the upper surface of the wiring (16) and a region not covered with the wiring (16) on the upper surface of the first insulating film (14); and forming a second insulating film (18) that covers the wiring (16).

A method of manufacturing a semiconductor wafer having a roughened metallization layer surface is described. The method includes immersing the semiconductor wafer in an electrolytic bath. Gas bubbles are generated in the electrolytic bath. A surface of a metallization layer on the semiconductor wafer is electrochemically roughened in the presence of the gas bubbles by applying a reversing voltage between the metallization layer and an electrode of the electrolytic bath.

A semiconductor storage device according to an embodiment includes: an array chip having a memory cell array; a circuit chip having a circuit electrically connected to a memory cell; and a metal pad bonding the array chip and the circuit chip together. The metal pad includes an impurity. A concentration of the impurity is lowered as separating in a depth direction apart from a surface in a thickness direction of the metal pad.

A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.