A power module includes: an insulating layer; a first metallic plate disposed on the insulating layer; a first semiconductor chip disposed on the first metallic plate; a first adhesive insulating layer and a second adhesive insulating layer disposed on the first metallic plate; a first metallic land for main electrode wiring disposed on the first adhesive insulating layer; and a first metallic land for signal wiring disposed on the second adhesive insulating layer. There can be provided a power module having reduced cost, reduced warpage of the whole of a substrate, stabilized quality, and improved reliability; and a fabrication method for such a power module.

The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.

A semiconductor device includes a first insulating substrate and a first semiconductor element joined to the first insulating substrate through the first conductive spacer. The first insulating substrate includes a first insulating layer and a first inner conductive layer disposed at a side of the first insulating layer. The first inner conductive layer includes a surface having a first region and a second region. The second region surrounds the first region and has larger surface roughness than the first region. The first conductive spacer is joined to the first region of the first inner conductive layer through a first junction layer.

A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction. The first/second terminals are connected to the first/second terminal portions, respectively.

A semiconductor module includes a semiconductor device and bus bar. The device includes an insulating substrate, conductive member, switching elements, and first/second input terminals. The substrate has main/back surfaces opposite in a thickness direction, with the conductive member disposed on the main surface. The switching elements are connected to the conductive member. The first input terminal, including a first terminal portion, is connected to the conductive member. The second input terminal, including a second terminal portion overlapping with the first terminal portion in the thickness direction, is connected to the switching elements. The second input terminal is separate from the first input terminal and conductive member in the thickness direction. The bus bar includes first/second terminals. The second terminal, separate from the first terminal in the thickness direction, partially overlaps with the first terminal in the thickness direction. The first/second terminals are connected to the first/second terminal portions, respectively.

A semiconductor device includes a lead, a first semiconductor element, and a sealing resin that covers at least a portion of each of the lead and the first semiconductor element. The lead has an obverse surface on which the first semiconductor element is mounted, and a reverse surface opposite to the obverse surface. The lead includes a first portion having a first surface. The first surface is located between the obverse surface and the reverse surface in the z direction in which the obverse surface and the reverse surface are separated from each other. The first surface of the lead is covered with the sealing resin, and is configured with a plurality of protruding areas and a plurality of recessed areas arranged alternately as viewed in the z direction.

Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

Provided is a coupled semiconductor package including at least two substrate pads; at least one semiconductor chip installed on each of the substrate pads; at least one terminal each of which is electrically connected to each substrate pad and each semiconductor chip; and a package housing covering a part of the at least one semiconductor chip and the at least one terminal, wherein lower surfaces of one or more substrate pads are formed to be electrically connected and lower surfaces of another one or more substrate pads are formed to be electrically insulated. Accordingly, partial insulation may be economically realized without applying an insulating material to a heat sink, when the package is joined to the heat sink.

A semiconductor device according to an embodiment is attached to a radiator and includes a heat-generating electronic component, a sealing part sealing the electronic component, a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part, and a lead member that includes an inner lead part sealed with the sealing part and an outer lead part exposed from the sealing part. The inner lead part has a heat-dissipating end part that releases heat propagating from the outer lead part to the radiator and an electrical connecting part that is positioned between the heat-dissipating end part and the outer lead part and is electrically connected to the main electrode of the electronic component.