A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.

A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region that is electrically conductive.

A semiconductor package structure is provided. The semiconductor package structure includes a lead frame and passive component. The lead frame includes a paddle and a plurality of leads. The lead frame includes a first surface and a second surface opposite to the first surface. The passive component includes an external connector. A pattern of the external connector is corresponding to a pattern of the plurality of leads of the lead frame.

In one example, an electronic device includes a substrate with a conductive structure and a substrate encapsulant. The conductive structure has a lead with a lead via and a lead protrusion. The lead via can include via lateral sides defined by first concave portions and the lead protrusion can include protrusion lateral sides defined by second concave portions. The substrate encapsulant covers the first concave portions at a first side of the substrate but not the second concave portions so that the lead protrusion protrudes from the substrate encapsulant at a second side of the substrate. An electronic component can be adjacent to the first side of the substrate and electrically coupled to the conductive structure. A body encapsulant encapsulates portions of the electronic component and the substrate. In some examples, the lead can further include a lead trace at the second side of the substrate. In some examples, the substrate can include a redistribution structure at the first side of the substrate. Other examples and related methods are also disclosed herein.

A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.

A method includes providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.

A wiring substrate includes a first metal plate and a second electrode. The first metal plate includes a first electrode, a wiring, and a mount portion for an electronic component. The mount portion includes an upper surface of the wiring. The second electrode is joined to an upper surface of the first electrode. The first electrode is solid. The second electrode is solid.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.

A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.