Patent classifications
H01L23/49558
LEAD FRAME ASSEMBLY
A lead frame assembly includes a lead frame body, an encapsulant unit, and dicing positioning units. The lead frame body includes lead frame units, an outer frame portion extending around the lead frame units, and through holes formed on the outer frame portion. The encapsulant unit includes a lower encapsulating portion, and an upper encapsulating portion formed on the lower encapsulating portion. The dicing positioning units are respectively located at the through holes, and each includes an adhesive layer which partially fills a corresponding one of the through holes and which is formed with at least one dicing positioning hole. The dicing positioning units define at least one first dicing positioning line and at least one second dicing positioning line.
Wiring substrate, method of manufacturing the same and electronic component device
A wiring substrate includes an electronic component mounting pad, an electrode pad arranged at an outer side of the electronic component mounting pad, a first insulation layer formed on the electronic component mounting pad and the electrode pad, an opening formed in the first insulation layer on the electronic component mounting pad, a connection hole formed in the first insulation layer on the electrode pad, and recess portions formed at the electronic component mounting pad in the opening and at the electrode pad in the connection hole, respectively.
SIGNAL BLOCK AND DOUBLE-FACED COOLING POWER MODULE USING THE SAME
A signal block and a double-faced cooling power module that uses the signal block is provided. The signal block includes a plurality of signal clips that are formed in a ribbon shape to connect a first signal pad formed on a semiconductor chip and a second signal pad formed on a signal lead frame. An insulator fixes the position of the plurality of signal clips while spacing the signal clips apart from each other.
Chip carrier structure, chip package and method of manufacturing the same
Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material.
Electronic component package including electronic component, metal member, and sealing resin
An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second principal surface, an electronic component disposed on the first principal surface and electrically connected to the metal pattern layer, at least one metal member disposed on the first principal surface and electrically connected to the metal pattern layer, a sealing resin layer disposed on the first principal surface, the electronic component and the at least one metal member, and an insulating layer disposed on the second principal surface. The at least one metal member is thicker than the electronic component. In plan view, the at least one metal member is disposed on an area of the first principal surface, the area including an end of the first principal surface. The at least a part of the metal pattern layer is exposed from the insulating layer.
POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE
A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.
Lead frame and a method of fabrication thereof
Disclosed is a method of manufacturing a lead frame, which comprises the steps of: providing an electrically-conductive base material having first and second planar sides; forming a plurality of conductive contact points on the first planar side of the base material; providing a non-conductive filling material over the first planar side of the base material so that the filling material fills spaces in-between the plurality of contact points to a form a layer comprising the filling material and the plurality of contact points; and etching the second planar side of the base material to expose a pattern of the filling material from the second planar side of the base material and to thereby form a plurality of isolated conductive regions on the second planar side of the base material, each isolated conductive region being connected with at least a respective one of the plurality of contact points on the first planar side of the base material. A lead frame structure is also disclosed.
Semiconductor package with multiple molding routing layers and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
Leadframe For A Semiconductor Component
The present disclosure relates to semiconductor components. The teachings thereof may be embodied in a lead frame for a semiconductor component including: a frame having a recess; an electrically conductive connecting element for establishing an electrical connection to the semiconductor component arranged in the recess; and an insulating element arranged in the recess and mechanically connecting the connecting element to the frame and electrically insulating it from the frame.
ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE
An electronic heat-dissipating substrate including: lead frames of wiring pattern shapes on a conductor plate; and an insulating member between the lead frames. A plate surface of the lead frames and a top surface of the insulating member form one continuous surface. The part arrangement surface is on both surfaces of the electronic part mounting heat-dissipating substrate, a reductant circuit which includes at least similar dual-system circuit is formed on the electronic part mounting heat-dissipating substrate, a first-system circuit of the dual-system circuit is formed on a first surface of the electronic part mounting heat-dissipating substrate, a second-system circuit of the dual-system circuit is formed on a second surface of the electronic part mounting heat-dissipating substrate, and the common lead frames used in a portion of a circuit wiring are used to the first surface and the second surface of the electronic part mounting heat-dissipating substrate.