A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.

A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.

A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

A semiconductor device and method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.

A lead frame includes a plurality of lead frame units. An upper surface of each of the plurality of lead frame units includes a soldering region and a non-soldering region outside of the soldering region. The non-soldering region includes a rough surface, and the soldering surface includes no rough surface. Each of the plurality of lead frame units may include a base island and a plurality of pins arranged around the base island, and the soldering region may be arranged on the base island and/or on the plurality of pins. The soldering region my include a wire-bonding soldering portion that connects to a chip via a bonding wire. Each of the plurality of lead frame units may include a plurality of pins, and the soldering region and the non-soldering region are arranged on the plurality of pins.

This disclosure relates to a flank wettable semiconductor device, having: a lead frame including a plurality of leads with a lead end portion and a semiconductor die mounted on the lead frame. The lead end portion comprises a recess portion having a height that corresponds to a thickness of the lead end portion, and a plate member mounted on the leadframe at the lead end portion.

A leadframe is formed by chemically half-etching a sheet of conductive material. The half-etching exposes a first side surface of a first contact of the leadframe. A solder wettable layer is plated over the first side surface of the first contact. An encapsulant is deposited over the leadframe after plating the solder wettable layer.

In one embodiment, a pre-product is configured for an electronic device intended to be loaded with a maximum current of at least 10 A, and comprises: an electronic component, a plurality of power terminals for external electrical contacting the electronic device, and a slide rail at an end of the at least one assigned power terminal remote from the electronic component. The power terminals are electrically connected to the electronic component and extend in a direction away from the electronic component. The slide rail is integrated in a metallic first leadframe together with at least one of the power terminals. A weight of the pre-product is at least 0.1 kg.

A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.