In one example, circuitry is formed in a semiconductor die. A magnetic concentrator is formed on a surface of the semiconductor die and over the circuitry. An isolation spacer is placed on a lead frame. The semiconductor die is placed on the isolation spacer, and the magnetic concentrator is aligned to overlap the lead frame. Electrical interconnects are formed between the semiconductor die and the lead frame.

In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of t.sub.press1>t.sub.cast1 and t.sub.press2>t.sub.cast1, where t.sub.press1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, t.sub.press2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and t.sub.cast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.

A method includes performing a non-screen printing process that deposits solder on a lead frame or on conductive features of a semiconductor die or wafer, or on or in a conductive via of a laminate structure. The method further comprises engaging the semiconductor die to the lead frame, performing a thermal process that reflows the solder, performing a molding process that forms a package structure which encloses the semiconductor die and a portion of the lead frame, and separating a packaged electronic device from a remaining portion of the lead frame.

A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting the terminal of the semiconductor chip and the lead frame. A mold resin layer encloses the semiconductor chip and the bonding wire, such that a portion of the lead frame extends out of the mold resin layer. A molecular bonding layer has a portion on a surface of the bonding wire and includes a first molecular portion covalently bonded to a material of the bonding wire and a material of the mold resin layer.

A semiconductor device includes a base, a semiconductor chip on the base, a conductive bonding layer between a surface of the base and a surface of the semiconductor chip, the conductive bonding layer including a resin and a plurality of conductive particles contained in the resin, and a molecular bonding layer between the surface of the semiconductor chip and a surface of the conductive bonding layer, and including a molecular portion covalently bonded to a material of the semiconductor chip and a material of the conductive bonding layer.

The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

A component with a semiconductor body, and first and second metal layer is disclosed. The first metal layer is arranged between the semiconductor body and the second metal layer, the semiconductor body has a first semiconductor layer on a side which is averted from the first metal layer, a second semiconductor layer on a side facing towards the first metal layer, and an active layer arranged between the first semiconductor layer and the second semiconductor layer, the component has a through-connection, which extends through the second semiconductor layer and the active layer for the electrical bonding of the first semiconductor layer. The second metal layer has a first subregion electrically connected to the through-connection by the first metal layer, and a second subregion spaced apart laterally from the first subregion by an intermediate space. In an overhead view, the first metal layer laterally completely covers the intermediate space.