A leadframe for a semiconductor device includes an array of electrically-conductive leads. The electrically-conductive leads have mutually opposed lateral (vertical) surfaces. An electrically-insulating material is formed over the mutually lateral opposed surfaces to prevent short circuits between adjacent leads. The electrically-insulating material may further be provided at one or more of the opposed bottom and top surfaces of the electrically-conductive leads of the leadframe.

A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m.Math.k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.

The present invention relates to a chip-on film type semiconductor package including an integrated circuit chip, a printed circuit board layer, an outer lead bonder pad, and a graphite layer, in which the integrated circuit chip is connected to one surface of the printed circuit board layer directly or by means of a mounting element, the outer lead bonder pad is located on one surface of the printed circuit board layer, and the graphite layer is laminated on an opposite surface of the printed circuit board layer and a display device including the same.

An interconnect structure may include a graphene-metal barrier on a substrate and a conductive layer on the graphene-metal barrier. The graphene-metal barrier may include a plurality of graphene layers and metal particles on grain boundaries of each graphene layer between the plurality of graphene layers. The metal particles may be formed at a ratio of 1 atom % to 10 atom % with respect to carbon of the plurality of graphene layers.

A component carrier with a double layer structure is illustrated and described. The double layer structure includes an electrically conductive patterned layer structure and a further patterned layer structure made of a two-dimensional material. The patterned layer structure and the further patterned layer structure have at least partly the same pattern. In an embodiment the component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure and at least one double layer structure connected with the stack.

Embodiments relate to the fabrication of an interposer with nanofibers by an additive process to electrically connect two or more electronic components. The nanofibers are grown on a substrate away from a surface of the substrate. The nanofibers are plated with a conductive material such that the nanofibers are encompassed in a column of the conductive material. An insulative material fills at least the volume between the columns of conductive material. The substrate and the interposer is the remaining device. The interposer can be combined with a redistribution layer to connect electronic components of dissimilar pitch.

A component carrier includes a stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component which is embedded in the stack and a stabilizing structure arranged between a stack surface of the stack and a main surface of the component. The stabilizing structure provides an interface adhesion to the main surface of the component.

An electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall of the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative coefficient of thermal expansion (CTE).

Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

There is provided a component carrier comprising: (a) a stack of at least one electrically conductive layer structure and at least one electrically insulating layer structure; and (b) a bypass capacitance structure formed on an/or within the stack. The bypass capacitance structure comprises an electrically conductive film structure having a rough surface, a dielectric film structure formed on the rough surface, and a further electrically conductive film structure formed on the dielectric film structure.