H01L27/14698

Manufacturing method of image sensing device

A manufacturing method of an image sensing device includes the following steps. A substrate is provided. At least one image sensing unit is disposed in the substrate. A passivation layer is formed on the substrate. An auxiliary layer is formed on the passivation layer. A material composition of the auxiliary layer is different from a material composition of the passivation layer. An annealing process is performed to the substrate and the passivation layer. The passivation layer is covered by the auxiliary layer during the annealing process. The auxiliary layer is removed after the annealing process. The ability to constrain and/or passivate free charge in and/or near the passivation layer may be enhanced by performing the annealing process with the auxiliary layer covering the passivation layer. The electrical performance of the image sensing device may be improved accordingly.

THROUGHPUT-SCALABLE ANALYTICAL SYSTEM USING TRANSMEMBRANE PORE SENSORS
20210293745 · 2021-09-23 · ·

The present disclosure describes a throughput-scalable sensing system. The system includes a plurality of semiconductor dies sharing a common semiconductor substrate and a plurality of transmembrane pore based sensors configured to detect a change of current flow as a result of analyzing biological or chemical samples. Two immediately neighboring transmembrane pore based sensors are arranged on respective two semiconductor dies separated by a dicing street. Each transmembrane pore based sensor is arranged on a separate semiconductor die of the plurality of semiconductor dies. At least one transmembrane pore based sensor includes one or more detection electrodes disposed above the common semiconductor substrate and a lipid bilayer disposed above the one or more detection electrodes.

THROUGHPUT-SCALABLE ANALYTICAL SYSTEM USING SINGLE MOLECULE ANALYSIS SENSORS
20210293746 · 2021-09-23 · ·

The present disclosure describes a throughput-scalable photon sensing system. The system includes a plurality of semiconductor dies sharing a common semiconductor substrate and a plurality of photon detection sensors configured to perform a single molecule analysis of biological or chemical samples. Two immediately neighboring photon detection sensors are arranged on respective two semiconductor dies separated by a dicing street. Each photon detection sensor is arranged on a separate semiconductor die. The system further includes a first optical waveguide, a plurality of second optical waveguides disposed above the first optical waveguide, one or more wells disposed in the plurality of second optical waveguides, and one or more light guiding channels.

METHOD FOR FABRICATING A THROUGHPUT-SCALABLE ANALYTICAL SYSTEM FOR MOLECULE DETECTION AND SENSING
20210296380 · 2021-09-23 · ·

A method for fabricating a throughput-scalable sensing system is disclosed. The method includes receiving a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a semiconductor substrate and a plurality of sensors disposed in the semiconductor substrate. Each sensor of the plurality of sensors is disposed in a separate semiconductor die of the first semiconductor wafer. The method further includes bonding the first semiconductor wafer to the second semiconductor wafer and preparing the bonded first semiconductor wafer and the second semiconductor wafer for conductive path redistribution. The method further includes forming one or more redistribution paths and dicing an array of semiconductor dies as a group from the plurality of semiconductor dies. The array of semiconductor dies includes a group of sensors associated with the throughput-scalable sensing system.

DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FABRICATION THEREOF

A Deep Trench Isolation (DTI) structure is disclosed. The DTI structures according to embodiments of the present disclosure include a composite passivation layer. In some embodiments, the composite passivation layer includes a hole accumulation layer and a defect repairing layer. The defect repairing layer is disposed between the hole accumulation layer and a semiconductor substrate in which the DTI structure is formed. The defect repairing layer reduces lattice defects in the interface, thus, reducing the density of interface trap (DIT) at the interface. Reduced density of interface trap facilitates strong hole accumulation, thus increasing the flat band voltage. In some embodiments, the hole accumulation layer according to the present disclosure is enhanced by an oxidization treatment.

METHOD OF FORMING IMAGE SENSOR DEVICE

A method includes providing a semiconductor substrate having a front side surface and a back side surface opposite to the front side surface. A photosensitive region of the semiconductor substrate is etched to form a recess. A semiconductor material is deposited on the semiconductor substrate to form a radiation sensing member filling the recess. The semiconductor material has an optical band gap energy smaller than 1.77 eV. A device layer is formed over the front side surface of the semiconductor substrate and the radiation sensing member. A trench isolation is formed in an isolation region of the semiconductor substrate and extending from the back side surface of the semiconductor substrate.

IMAGING DEVICE AND METHOD OF MANUFACTURING IMAGING DEVICE
20210175277 · 2021-06-10 · ·

To increase the capacity of a charge holding section of a pixel in an imaging device that performs imaging using a global shutter method. An imaging device includes a photoelectric converter, a first charge holding section, an auxiliary charge holding section, a transfer route, and an image signal generator. The first charge holding section is formed near a front surface of a semiconductor substrate. A first charge transfer section transfers charge from the photoelectric converter to the first charge holding section. The auxiliary charge holding section underlies the first charge holding section, and holds a portion of the charges held in the first charge holding section. The transfer route transfers the charge between the first charge holding section and the auxiliary charge holding section. The image signal generator generates an image signal based on the charges held in the first charge holding section and the auxiliary charge holding section.

Metal vertical transfer gate with high-k dielectric passivation lining

A method for manufacturing an image sensor includes, for each of a plurality of photosensitive pixels of the image sensor, forming a trench in a semiconductor substrate of the image sensor, and depositing temporary transfer gate material in and above the trench. The method further includes, after the step of depositing temporary transfer gate material, high-temperature annealing at least a portion of the semiconductor substrate. In addition, the method includes, after the step of high-temperature annealing, (a) removing the temporary transfer gate material, thereby reopening the trench, (b) depositing a passivation lining, having a high-k dielectric, in the reopened trench, and (c) depositing metal on the high-k dielectric passivation lining to form a metal vertical transfer gate in the trench and extending above the trench.

FULL WELL CAPACITY FOR IMAGE SENSOR
20210273123 · 2021-09-02 ·

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region having a first doping type. A deep well region is disposed within the semiconductor substrate, where the deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a first dopant having a second doping type opposite the first doping type, where the first dopant comprises gallium.

IMAGE DEVICE AND FABRICATING METHOD THEREOF
20210175266 · 2021-06-10 ·

An image device includes a first active region and a second active region disposed on a substrate. Each of the first active region and the second active region includes a gate insulating layer disposed on the substrate and a gate electrode disposed on the gate insulating layer. At least one of the first active region and the second active region further includes a first passivation layer containing fluorine (F) disposed between the gate insulating layer and the gate electrode. A concentration of fluorine in the gate insulating layer is higher than a concentration of fluorine in the gate electrode.