Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.

An IC device includes capacitor elements formed within the same wiring level and in an area of the wiring level that is between a pair of wiring lines. This area may be an area that is not previously utilized, may be an area where dummy metal features were traditionally utilized, or the like. In a first implementation, the capacitor elements include a first capacitor comb interleaved with a second capacitor comb. In another implementation, the capacitor element is a perforated capacitor plate. The geometry of the interleaved capacitor combs and the open area of the perforations may be tuned in order to achieve or meet a predetermined uniform wiring level metal density requirement(s). The IC device may utilize a capacitor formed at least in part with the capacitor elements as a decoupling capacitor, a noise filter, a sensor, or the like.

Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

An integrated electronic component for broadband biasing that includes a monolithic substrate, a capacitor structure arranged in a trench network that extends into the substrate, and a continuous track of an electrically conducting material arranged in a crater that is formed in the substrate. The continuous track has one or several turns that have decreasing turn sections, and that are supported by a slanted peripheral wall of the crater for forming an inductor.

Embodiments are directed to a method and resulting structures for forming low resistance, high capacitance density MIM capacitors. In a non-limiting embodiment, one or more bottom plate contacts are formed over a substrate. A bottom capacitor plate is formed directly on a top surface and a sidewall of each of the one or more bottom plate contacts. A capacitor dielectric layer is formed directly on a surface of the bottom capacitor plate. A top capacitor plate is formed directly on a surface of the capacitor dielectric layer. A first portion of the top capacitor plate extends past a sidewall of the bottom capacitor plate in a direction parallel to the substrate. A top plate contact is formed directly on the first portion of the top capacitor plate.

An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.

A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.

The present disclosure provides a semiconductor capacitor structure. The semiconductor capacitor structure includes a substrate, a comb-like bottom electrode disposed over the substrate, a top electrode disposed over the comb-like bottom electrode, and a dielectric layer sandwiched between the top electrode and the comb-like bottom electrode. The comb-like bottom electrode includes a plurality of tooth portions parallel to the substrate and a supporting portion coupled to the plurality of tooth portions and perpendicular to the substrate.