A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.

Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

A semiconductor structure and a method for forming same are provided. The forming method includes: forming a second electrode layer on a first dielectric layer, where the second electrode layer covers the first dielectric layer in a first region; forming a second dielectric layer on a second electrode layer and in a second region; forming a third electrode layer on the second dielectric layer, where on a projection plane parallel to the base, the third electrode layer has an overlapping region with each of the first region and the second region; and forming a first electrically connecting structure in contact with the second electrode layer, and forming, in the second region, a second electrically connecting structure in contact with the third electrode layer and the first electrode layer; or forming a third electrically connecting structure in contact with the first electrode layer, and forming a fourth electrically connecting structure in contact with the second electrode layer and the third electrode layer. By adjusting a connection relationship between different electrode layers, different equivalent capacitance densities can be obtained, thereby satisfying demands of different types of capacitors.

A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.

A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 110a and a second capacitor electrode layer 110b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 110a and the second capacitor electrode layer 110b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 110a and a second capacitor electrode layer 110b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 110a and the second capacitor electrode layer 110b; and a through-substrate via conductor 116.

A solid-state device includes a substrate with a stack of constituent thin-film layers that define an arrangement of electrodes and intervening layers. The constituent layers can conform to or follow a non-planar surface of the substrate, thereby providing a 3-D non-planar geometry to the stack. Fabrication employs a common shadow mask moved between lateral positions offset from each other to sequentially form at least some of the layers in the stack, whereby layers with a similar function (e.g., anode, cathode, etc.) can be electrically connected together at respective edge regions. Wiring layers can be coupled to the edge regions for making electrical connection to the respective subset of layers, thereby simplifying the fabrication process. By appropriate selection and deposition of the constituent layers, the multi-layer device can be configured as an energy storage device, an electro-optic device, a sensing device, or any other solid-state device.

The present invention relates to a capacitor and its formation method and to a DRAM cell. In various embodiments, a substrate is provided such that an electrical contact portion is formed thereon. A dielectric layer is formed on a surface of the substrate, including alternately stacked supporting layers and sacrificial layers. At least two capacitor holes penetrating the sacrificial layers and the supporting layers can formed to expose the same electrical contact portion. A lower electrode layer covering the inner surface of the capacitor holes can be formed. The lower electrode layer is connected to the electrical contact portion. The sacrificial layers are then removed and a capacitor dielectric layer and an upper electrode layer are formed successively on the inner and outer surfaces of the lower electrode layer and on the surface of the supporting layers. This can increase capacitance value per unit area of the capacitor.

A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.

The present disclosure provides a semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of storage node pads, a supporting structure, and a capacitor structure. The storage node pads are disposed on the substrate. The supporting structure is disposed on the substrate and includes a first supporting layer and a second supporting layer from bottom to top. The capacitor structure is disposed on the substrate, and the capacitor structure includes columnar bottom electrodes, a capacitor dielectric layer and a top electrode layer stacked from bottom to top, wherein the columnar bottom electrodes include a first columnar bottom electrode having a symmetric columnar structure and a second columnar bottom electrode having an asymmetric columnar structure, and the first columnar bottom electrode and the second columnar bottom electrode respectively include at least one horizontal extending portion along a horizontal direction.

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.