A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

A capacitor includes a structure including a plurality of openings penetrating from a first surface of the structure to a second surface opposing the first surface; a capacitor layer disposed on the second surface of the structure and in the plurality of the openings and including a dielectric layer, and a first electrode and a second electrode, the dielectric layer interposed between the first electrode and the second electrode; a first connection layer disposed on the first surface of the structure and connected to the first electrode; a second connection layer disposed on the capacitor layer on the second surface and connected to the second electrode of the structure; and first and second terminals disposed on opposite side surfaces of the structure and connected to the first connection layer and the second connection layer, respectively.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.

Horizontal-trench on-chip capacitors are provided. In one aspect, a method of forming a capacitor includes: forming alternating sacrificial/active nanosheets on a wafer; patterning the nanosheets into a fin stack(s); burying the fin stack(s) in an ILD; removing the ILD from a first side of the fin stack(s), forming a first cavity; filling the first cavity with a semiconductor material that interconnects the nanosheets of the active material; implanting ions into the nanosheets, semiconductor material and wafer; removing the ILD from a second side of the fin stack(s) forming a second cavity; selectively removing the nanosheets of the sacrificial material, creating gaps between the nanosheets of the active material; depositing a dielectric into/lining the gaps and second cavity; and filling the gaps and second cavity with a conductor. A capacitor is also provided.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

The subject application relates to a semiconductor package device, which includes a first conductive layer; a semiconductor wall disposed on the first conductive layer; a first conductive wall disposed on the first conductive layer; and an insulation layer disposed on the first conductive layer and between the semiconductor wall and the first conductive wall.