A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.

Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

A method for forming a capacitor includes: providing a substrate; sequentially forming a first sacrificial layer and a first support layer for covering the substrate; forming first openings penetrating through the first support layer; sequentially forming a second sacrificial layer and a second support layer for covering a remaining portion of the first support layer; forming through holes which sequentially penetrate through the second support layer, the second sacrificial layer, the remaining portion of the first support layer, and the first sacrificial layer; forming first electrode layers, each first electrode layer covering an inner wall of a respective one of the through holes; forming second openings penetrating through a remaining portion of the second support layer; and sequentially forming a dielectric layer and a second electrode layer for covering the first electrode layers, to form the capacitor.

An approach provides a metal-insulator-metal capacitor with a comb-like structure. The metal-insulator-metal capacitor includes a first electrode material forming a central, vertical portion of the first electrode metal and two sets of stacked horizontal portions of the first electrode metal. An insulator material surrounds the first electrode metal and exposes a top surface of the central, vertical portion of the first electrode metal. The metal-insulator-metal capacitor includes a second electrode material surrounding the insulator material. The metal-insulator-metal capacitor includes a first electrode contact connecting to the top surface of the central, vertical portion of the first electrode metal and a second electrode contact connecting to a top surface of the second electrode material.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: forming a capacitor on a substrate, where a first support layer is provided between parts of the first electrodes in the capacitor away from the substrate; removing part of a second electrode and part of a first dielectric layer to expose a surface of the first support layer away from the substrate; forming, on the surface of the first support layer away from the substrate, a second support layer having a first hole structure; forming, on a side surface of the first hole structure, a third electrode in contact with the first electrode; forming a second dielectric layer covering the third electrode and being in contact with the first dielectric layer; and forming, on a side surface of the second dielectric layer, a fourth electrode in contact with the second electrode.

Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.