The present invention relates to a capacitor and its formation method and to a DRAM cell. In various embodiments, a substrate is provided such that an electrical contact portion is formed thereon. A dielectric layer is formed on a surface of the substrate, including alternately stacked supporting layers and sacrificial layers. At least two capacitor holes penetrating the sacrificial layers and the supporting layers can formed to expose the same electrical contact portion. A lower electrode layer covering the inner surface of the capacitor holes can be formed. The lower electrode layer is connected to the electrical contact portion. The sacrificial layers are then removed and a capacitor dielectric layer and an upper electrode layer are formed successively on the inner and outer surfaces of the lower electrode layer and on the surface of the supporting layers. This can increase capacitance value per unit area of the capacitor.

A capacitor and a method of fabricating the capacitor are provided. The capacitor includes a structure for forming a three-dimensional capacitor, the structure being a pillar structure or a trench structure; where when the structure is a pillar structure, the aspect ratio of the pillar structure is more than 10; when the structure is a trench structure, the capacitor further includes a substrate, the trench structure is formed by a material layer disposed on the surface of a base trench of the substrate, and the aspect ratio of the trench structure is more than 10. The aspect ratio of the pillar structure of the capacitor or the aspect ratio of the trench structure may be more than 10, so that the performance of the capacitor is better.

A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

The present application provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate; disposing a first insulating layer over the semiconductor substrate; disposing a first bottom electrode over the first insulating layer; disposing a first dielectric layer over the first bottom electrode; removing a portion of the first dielectric layer to form a first recess extending through the first dielectric layer; disposing a first capacitor dielectric conformal to the first recess and over the first bottom electrode; and forming a first top electrode within the first recess and surrounded by the first capacitor dielectric, wherein the first capacitor dielectric and the first top electrode extend laterally over the first bottom electrode and the semiconductor substrate.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a lower supporting layer on the substrate; forming an upper supporting layer on the lower supporting layer, wherein the upper supporting layer defines an opening; and forming a lower electrode within the opening of the upper supporting layer, wherein the lower electrode has a first portion with a first vertical length and a second portion with a second vertical length different from the first vertical length.

The present disclosure provides a semiconductor structure and a production method thereof so that a non-linear trench structure can be produced, which can increase a surface area of the trench structure without increasing an aspect ratio and maintaining the same footprint. The semiconductor structure includes: a substrate including an upper surface and a lower surface disposed opposite to each other; and at least one trench structure disposed in the substrate and formed downward from the upper surface, where the trench structure is projected on the upper surface to form a first pattern in a curved or broken line shape, and the first pattern includes n second patterns adjacent to each other, and in the n second patterns, odd-numbered second patterns are the same, and even-numbered second patterns are the same, where n is a positive integer.

The disclosure is directed to semiconductor structures and, more particularly, to Metal-Insulator-Metal (MIM) capacitor structures and methods of manufacture. The method includes: forming at least one gate structure; removing material from the at least one gate structure to form a trench; depositing capacitor material within the trench and at an edge or outside of the trench; and forming a first contact in contact with a first conductive material of the capacitor material and a second contact in contact with a second conductive material of the capacitor material.

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

A digital integrated circuit includes first areas of a substrate which incorporate digital functions and second areas of the substrate which are filler between first areas. A capacitance is provided by interdigitated metal-insulator-metal structures formed from a metallization level above the substrate. The structures of the capacitance are vertically aligned with one or more of the second areas.