Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

An interdigitated capacitor includes a substrate and a pair of comb-like electrodes both formed on the semiconductor substrate and horizontally arranged thereon, each of the pair of comb-like electrodes including finger electrodes having a curved profile.

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

A method used in forming integrated circuitry comprises forming an array of structures elevationally through a stack comprising first and second materials. The structures project vertically relative to an outermost portion of the first material. Energy is directed onto vertically-projecting portions of the structures and onto the second material in a direction that is angled from vertical and that is along a straight line between immediately-adjacent of the structures to form openings into the second material that are individually between the immediately-adjacent structures along the straight line. Other embodiments, including structure independent of method, are disclosed.

Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.

The present description concerns a capacitor manufacturing method, including the successive steps of: a) forming a stack including, in the order from the upper surface of a substrate, a first conductive layer made of aluminum or an aluminum-based alloy, a first electrode, a first dielectric layer, and a second electrode; b) etching, by chemical plasma etching, an upper portion of the stack, said chemical plasma etching being interrupted before the upper surface of the first conductive layer; and c) etching, by physical plasma etching, a lower portion of the stack, said physical plasma etching being interrupted on the upper surface of the first conductive layer.

A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

A semiconductor device includes a stack including a plurality of electrode layers which include a plurality of capacitor first electrode layers and a plurality of capacitor second electrode layers alternately stacked on a substrate and a plurality of dielectric layers which are disposed alternately with the plurality of electrode layers; a first conductive pillar passing through the stack and coupled to the plurality of capacitor first electrode layers; a second conductive pillar passing through the stack and coupled to the plurality of capacitor second electrode layers; and a plurality of insulation layer patterns insulating the first conductive pillar and the plurality of capacitor second electrode layers from each other and insulating the second conductive pillar and the plurality of capacitor first electrode layers from each other.

A capacitor structure implemented as a layered structure including a plurality of alternating dielectric and metallization layers, and a method of manufacturing such capacitor structure. The capacitor structure including at least one lateral parallel plate capacitor part (LPP part) including two first electrodes on two different layers separated by dielectric material of a plurality of the alternating layers, and at least one vertical parallel plate capacitor part (VPP part) including two second electrodes each including a plurality of superimposed slabs or bars arranged on a plurality of the metallization layers. The at least one LPP part is electrically coupled with the at least one VPP part to form the capacitor structure. A variation in capacitance value of the at least one LPP part due to a variation of thickness of dielectric material is at least partially compensated by an opposite variation in capacitance value of the at least one VPP part.