A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.

A method for fabricating a semiconductor device, including the steps of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing a wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole.

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.

The present invention relates to an optoelectronic device comprising: (a) a substrate comprising at least one first electrode, which at least one first electrode comprises a first electrode material, and at least one second electrode, which at least one second electrode comprises a second electrode material; and (b) a photoactive material disposed on the substrate, which photoactive material is in contact with the at least one first electrode and the at least one second electrode, wherein the substrate comprises: a layer of the first electrode material; and, disposed on the layer of the first electrode material, a layer of an insulating material, which layer of an insulating material partially covers the layer of the first electrode material; and, disposed on the layer of the insulating material, the second electrode material, and wherein the photoactive material comprises a crystalline compound, which crystalline compound comprises: one or more first cations selected from metal or metalloid cations; one or more second cations selected from Cs.sup.+′RB.sup.+, K.sup.+, NH.sup.4 + and organic cations; and one or more halide or chalcogenide anions. A substrate comprising a first and second electrode and processes are also described.

A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

Disclosed are a display substrate, a display device, a manufacturing method and a repairing method. A capacitor structure in the display substrate includes a first electrode and a second electrode. The first electrode includes a first main body portion extending in a first direction, first branch portions extending in a second direction, and a first connection portion connecting the first branch portions to the first main body portion. The second electrode includes a second main body portion extending in the first direction, second branch portions extending in the second direction, and a second connection portion connecting the second branch portions to the second main body portion. One side of the first electrode having the first branch portions faces one side of the second electrode having the second branch portions, and each first branch portion and a corresponding second branch portion form a capacitor.

A device includes a main capacitor composed of a first plate of a first back-end-of-line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is composed of a second BEOL metallization layer. The device includes a first tuning capacitor of a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor through first BEOL sideline traces. The first tuning capacitor is composed of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.

A DRAM device and its manufacturing method are provided. The DRAM device includes an interlayer dielectric layer and capacitor units framed on a substrate. The interlayer dielectric layer has capacitor unit accommodating through holes and includes a first support layer, a composite dielectric layer, and a second support layer sequentially formed on the substrate. The composite dielectric layer includes at least one first insulating layer and second insulating layer alternately stacked. Each capacitor unit accommodating through hole forms a first opening in the second insulating layer and forms a second opening communicating with the first opening in the first insulating layer. The second opening is wider than the first opening. The capacitor units are formed in the capacitor unit accommodating through holes. The top of the capacitor unit is higher than the top surface of the interlayer dielectric layer and defines a recessed region.