A semiconductor device includes a substrate, a bottom electrode on the substrate, a first support layer on the substrate next to a sidewall of the bottom electrode, a dielectric layer covering the sidewall and a top surface of the bottom electrode, and a top electrode on the dielectric layer. The bottom electrode includes a first part having a plurality of protrusions that protrude from a sidewall of the first part. The first part of the bottom electrode may be on the first support layer.

The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

A manufacturing method of a semiconductor structure includes forming a dielectric layer stack including a first oxide layer and a second oxide layer over the first oxide layer. An opening is formed in the dielectric layer stack, and includes a first portion exposing sidewalls of the first oxide layer and a second portion exposing sidewalls of the second oxide layer. A sacrificial layer is formed over the dielectric layer stack and along the sidewalls of the first oxide layer and the second oxide layer in the opening. A first etching is performed to remove the sacrificial layer along the sidewalls of the first oxide layer. A second etching is performed to widen the first portion of the opening. The sacrificial layer along the sidewalls of the second oxide layer and over the dielectric layer stack is removed. A capacitor is formed in the opening after removing the sacrificial layer.

A semiconductor structure includes a substrate, a bottom metal structure located on the substrate, a first dielectric layer located on the bottom metal structure, first plug structures, second plug structures, and first metal structures. The substrate includes a base, a device structure located on the base, and conductive layers located on the device structure. The bottom metal structure is electrically connected to the conductive layers. The first dielectric layer includes a first opening structure and a second opening structure. The first opening structure includes first grooves and second grooves on top of the first grooves, and the second opening structure includes third grooves and fourth grooves on top of the third grooves. The first plug structures are located in the first grooves, and the second plug structures are located in the third grooves. The first metal structures are located in the second grooves and the fourth grooves.

Ferroelectric random access memory (FRAM) capacitors and methods of forming FRAM capacitors are provided. An FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of an FRAM memory cell. For example, an FRAM memory cell may include one FRAM capacitor and one transistor (1T1C configuration) or two FRAM capacitors and two transistor (2T2C configuration).

A semiconductor device includes a first electrode and a second electrode configuring a MIM capacitor. The first electrode includes a first via plug extending along a first direction. The second electrode includes a second lower wiring extending along the first direction and arranged side by side with the first via plug in a second direction. A length of the first via plug in the first direction is larger than a length of the first via plug in the second direction. A length of the second lower wiring in the first direction is larger than a length of the second lower wiring in the second direction. A length of the first via plug in a third direction is larger than a length of the second lower wiring in the third direction.

Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

A method of forming a semiconductor structure includes following steps. A substrate is provided. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. A poly layer is formed on the dielectric stack. The poly layer and the dielectric stack are etched to form an opening to expose the contact of the substrate. A conductive film is formed in the opening and an ALD oxide layer is deposited on a sidewall of the opening. In addition, a semiconductor structure is also disclosed herein.

A unit trench capacitor in a substrate includes one or more trenches in the substrate, a dielectric layer, a first electrode and a second electrode. Walls of the one or more trenches are covered by the dielectric layer which separates the first electrode from the second electrode. Each trench follows a closed curve. The closed curve of each trench has one or more elongated parts in directions in which the substrate has a maximum elastic modulus, or the closed curve of each trench has a circular shape if the substrate has an isotropic elastic modulus.

A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.